High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method

• US 10,297,594 B2
• Filed: 08/06/2015
• Issued: 05/21/2019
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lee, Yeeheng, Kim, Jongoh, Chang, Hong
• Primary Examiner(s): Chen, Yu
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US14/820,482
• Publication Number:
  US 20150340363A1
• Time in Patent Office: 1,384 Days
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

Claims

1. A high density trench-gated MOSFET device comprising:

a semiconductor substrate;

an epitaxial region overlaying the semiconductor substrate, a body region overlying the epitaxial region and a source region overlying the body region;

an array of active nitride-capped trench gate stacks (ANCTGS), with inter-ANCTGS separations, disposed above the semiconductor substrate and embedded vertically into the source region, the body region and the epitaxial region, wherein each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride cap covering a top surface of the polysilicon trench gate, wherein portions of the silicon nitride cap disposed on the top surface of the polysilicon trench gate is separated from the polysilicon trench gate, and laterally extending over edges of the gate oxide shell whereby forming, together with the source region, the body region and the epitaxial region, a MOSFET array;

a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region whereby the patterned metal layer forms, with the MOSFET array, a plurality of self-aligned source and body contacts through the inter-ANCTGS separations, wherein the top surface of the polysilicon trench gate extending to both sides of the gate oxide shell is above a top surface of the source region; and

a gate pickup area comprising;

a pickup nitride-capped trench gate stack (PNCTGS) disposed above the semiconductor substrate and embedded vertically into the epitaxial region, wherein the PNCTGS comprises a stack of polysilicon trench gate embedded in a gate oxide shell, wherein the polysilicon trench gate of the PNCTGS is routed to join the polysilicon trench gate of each ANCTGS; and

a pair silicon nitride cap with a center gap laterally registered to the gate oxide shell, the pair silicon nitride cap covers, except for the center gap, the top surface of the polysilicon trench gate whereby the patterned metal layer forms, through the center gap, a self-aligned gate contact to the top surface of polysilicon trench gate;

wherein the patterned metal layer contacts a top surface of the pair silicon nitride cap;

wherein a bottom surface of the patterned dielectric region is directly attached to a pad oxide region atop the source region;

wherein a portion of the pad oxide region is beneath the silicon nitride cap;

wherein the patterned dielectric region and the pad oxide region are made of different materials;

wherein the patterned dielectric region is directly attached to the silicon nitride cap; and

wherein a top surface of the patterned dielectric region is directly attached to the patterned metal layer.

2. The trench-gated MOSFET device of claim 1 further comprising:

atop the source region but beneath each silicon nitride cap, a pad oxide region throughout an area of the MOSFET array; and

atop the source region but beneath the pair silicon nitride cap, another pad oxide region throughout the gate pickup area.

3. The trench-gated MOSFET device of claim 2, wherein each silicon nitride cap of ANCTGS has a width of 0.3 to 1 micron and a thickness of 1000 to 5000 Angstroms, and wherein the pair silicon nitride cap of PNCTGS has a width of 0.5 to 1.6 microns measured from outer opposite edges across the center gap and a thickness of 1000 to 5000 Angstroms.

4. The trench-gated MOSFET device of claim 1 further comprising:

at a contact interface between the patterned metal layer and the source and body contacts, a first contact enhancement plug for improving quality and reliability of the contact interface between the patterned metal layer and the source and body contacts; and

at a contact interface between the patterned metal layer and the PNCTGS, a second contact enhancement plug for improving quality and reliability of the contact interface between the patterned metal layer and the PNCTGS.

5. The trench-gated MOSFET device of claim 4, wherein the first contact enhancement plug has a thickness of to 4000 Angstroms and comprises a titanium/titanium nitride (Ti/TiN) barrier layer and a tungsten (W) layer atop the Ti/TiN barrier layer.

6. The trench-gated MOSFET device of claim 1, wherein the polysilicon trench gate has an upper trench portion and a lower trench portion, and the gate oxide shell has an upper gate oxide shell and a lower gate oxide shell, a thickness of the lower gate oxide shell is larger than that of the upper gate oxide shell, whereby effecting a desired reduction of gate-to-drain capacitance of a corresponding MOSFET.

7. The trench-gated MOSFET device of claim 6, wherein

the upper trench portion of the polysilicon trench gate in the area of the MOSFET array has a width of 0.2 to 0.3 micron and a depth of 0.3 to 0.6 micron;

the lower trench portion of the polysilicon trench gate in the area of the MOSFET array has a depth of 0.3 to 0.6 micron;

the upper gate oxide shell has a thickness of 100 to 600 Angstroms; and

the lower gate oxide shell has a thickness of 300 to 1000 Angstroms.

8. The trench-gated MOSFET device of claim 1, wherein

the silicon nitride cap is directly attached to an upper portion of the gate oxide shell.

9. The trench-gated MOSFET device of claim 8, wherein the patterned dielectric region is directly attached to the pair silicon nitride cap.

10. The trench-gated MOSFET device of claim 9, wherein the pair silicon nitride cap is directly attached to an upper portion of the gate oxide shell of the PNCTGS.

11. The trench-gated MOSFET device of claim 10, wherein portions of the pair silicon nitride cap disposed on the top surface of the polysilicon trench gate of each PNCTGS is separated from the polysilicon trench gate of each PNCTGS, and laterally extending over edges of the gate oxide shell.

12. The trench-gated MOSFET device of claim 11, wherein bottom surfaces the portions of the pair silicon nitride cap separated from the polysilicon trench gate of each PNCTGS are at a position lower than a bottom surface of another portion of the silicon nitride cap of each PNCTGS directly attached to the polysilicon trench gate.

13. The trench-gated MOSFET device of claim 1, wherein bottom surfaces the portions of the silicon nitride cap separated from the polysilicon trench gate are at a position lower than a bottom surface of a center portion of the silicon nitride cap directly attached to the polysilicon trench gate.

14. The trench-gated MOSFET device of claim 1, wherein a contact enhancement plug fills at least a bottom portion of the center gap of the pair silicon nitride cap and wherein the patterned metal layer fills a top portion of the center gap of the pair silicon nitride cap.