Semiconductor device and manufacturing method of semiconductor device

• US 10,297,682 B2
• Filed: 01/30/2017
• Issued: 05/21/2019
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Shirakawa, Tohru, Takahashi, Hidenori
• Primary Examiner(s): Manno, Jessica
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US15/418,788
• Publication Number:
  US 20170141217A1
• Time in Patent Office: 841 Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Claims

1. A semiconductor device comprising:

a plurality of trench gates extending in a first direction in plan view;

a plurality of first-conductivity-type regions spaced away from each other in the first direction, the plurality of first-conductivity-type regions being shallower than the plurality of trench gates;

a plurality of second-conductivity-type regions alternating with the plurality of first-conductivity-type regions in the first direction, the plurality of second-conductivity-type regions being shallower than the plurality of trench gates and deeper than the plurality of first-conductivity-type regions; and

a second-conductivity-type trench spacer region spaced away from the plurality of trench gates, the second-conductivity-type trench spacer region having a higher concentration than the plurality of second-conductivity-type regions, wherein

the second-conductivity-type trench spacer region is positioned within the plurality of first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the plurality of first-conductivity-type regions are, and

a maximum depth of the second-conductivity-type trench spacer region that overlaps a given one of the plurality of first-conductivity-type regions in plan view is shallower than a maximum depth of the second-conductivity-type trench spacer region that overlaps one of the plurality of second-conductivity-type regions adjacent to the given one of the plurality of first-conductivity-type regions in plan view.

2. The semiconductor device as set forth in claim 1, wherein

a depth of the second-conductivity-type trench spacer region is equal to or less than half intervals between the plurality of trench gates.

3. The semiconductor device as set forth in claim 1, wherein

the plurality of trench gates are arranged at a pitch of less than 5 μ

m.

4. The semiconductor device as set forth in claim 3, wherein

the plurality of trench gates are arranged at a pitch of 2.4 μ

m or less.

5. The semiconductor device as set forth in claim 1, further comprising:

an insulating film formed on a front surface of the plurality of first-conductivity-type regions and having a contact opening therein that penetrates therethrough to reach the plurality of first-conductivity-type regions; and

a contact diffusion region formed in the contact opening and connected to the plurality of first-conductivity-type regions, wherein

in plan view, a portion of the second-conductivity-type trench spacer region that overlaps the given one of the plurality of first-conductivity-type regions is positioned within the contact opening.

6. The semiconductor device as set forth in claim 5, wherein

in plan view, an impurity concentration in a portion of the given one of the plurality of first-conductivity-type regions that is positioned within the contact opening is lower than an impurity concentration in a portion of the given one of the plurality of first-conductivity-type regions that abuts a corresponding one of the plurality of trench gates.

7. The semiconductor device as set forth in claim 1, wherein

a portion of the second-conductivity-type trench spacer region that overlaps the given one of the plurality of first-conductivity-type regions in plan view is connected to a portion of the second-conductivity-type trench spacer region that overlaps the one of the plurality of second-conductivity-type regions adjacent to the given one of the plurality of first-conductivity-type regions in plan view.

8. The semiconductor device as set forth in claim 1, wherein

a portion of the second-conductivity-type trench spacer region that overlaps the given one of the plurality of first-conductivity-type regions in plan view has a thickness of 0.1 mm or less.

9. The semiconductor device as set forth in claim 1, wherein

the plurality of first-conductivity-type regions each have a width of 1.4 μ

m or less in the first direction.

10. The semiconductor device as set forth in claim 1, wherein

maximum depths of the second-conductivity-type trench spacer region that overlaps the plurality of first-conductivity-type regions in plan view are substantially the same as one another.

11. The semiconductor device as set forth in claim 10,

wherein

maximum depths of the second-conductivity-type trench spacer region that overlaps the plurality of second-conductivity-type regions adjacent to the plurality of first-conductivity-type regions in plan view are substantially the same as one another.