Semiconductor device with a gate electrode positioned in a semiconductor substrate

• US 10,319,831 B2
• Filed: 02/25/2015
• Issued: 06/11/2019
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Onishi, Toru, Oki, Shuhei, Ikeda, Tomoharu, Tasbir, Rahman Md.
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US15/300,848
• Publication Number:
  US 20170033195A1
• Time in Patent Office: 1,567 Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a trench provided in a front surface of the semiconductor substrate;

a gate insulating film covering an inner surface of the trench; and

a gate electrode provided on an inner side of the gate insulating film, the gate electrode including a first layer and a second layer,

wherein

the first layer includes an outer portion of a front surface of the gate electrode,

the second layer includes a middle portion of the front surface,

the front surface of the gate electrode is provided at a position deeper than the front surface of the semiconductor substrate, and the middle portion of the front surface, which is located at a center in a width direction of the trench, is provided at a position shallower than the outer portion of the front surface, which is in contact with the gate insulating film,

the middle portion and the outer portion form a single, continuous surface, of the front surface, and

the outer portion is provided at a depth within 400 nm from the front surface of the semiconductor substrate.

2. The semiconductor device as in claim 1, further comprising:

a front surface semiconductor region of a first conductivity type exposed on the front surface of the semiconductor substrate;

a top body region of a second conductivity type provided at a position deeper than the front surface semiconductor region;

a barrier region of the first conductivity type provided at a position deeper than the top body region; and

a drift region of the first conductivity type having a lower first conductivity type impurity density than the barrier region, and provided at a position deeper than the barrier region,

wherein the trench penetrates the front surface semiconductor region, the top body region, and the barrier region, and

a lower end of the trench projects into the drift region.

3. The semiconductor device as in claim 2, further comprising:

a bottom body region provided at a position deeper than the barrier region and shallower than the drift region,

wherein the trench further penetrates the bottom body region.

4. The semiconductor device as in claim 1, wherein the first layer is provided with a phosphorus density higher than that of the second layer prior to a heat treatment of the gate electrode, such that the middle portion is more resistant to etching than the outer portion during formation of the front surface prior to the heat treatment of the gate electrode.

5. The semiconductor device as in claim 1, wherein the middle portion is positioned at a depth between the depth of the outer portion and the front surface of the semiconductor substrate.