Transistor-based radio frequency (RF) switch
First Claim
1. A transistor-based radio frequency (RF) switch comprising:
- an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five;
a gate bias network comprising;
a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled between gate terminals of adjacent ones of the N number of main FETs;
a common gate resistor coupled between a gate control input and a gate control node of the plurality of gate resistors; and
a first capacitor coupled between the gate control node and a switch path node of the N number of main FETs.
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Accused Products
Abstract
Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.
54 Citations
19 Claims
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1. A transistor-based radio frequency (RF) switch comprising:
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an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five; a gate bias network comprising; a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled between gate terminals of adjacent ones of the N number of main FETs; a common gate resistor coupled between a gate control input and a gate control node of the plurality of gate resistors; and a first capacitor coupled between the gate control node and a switch path node of the N number of main FETs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification