System and methods for extraction of threshold and mobility parameters in AMOLED displays

• US 10,325,537 B2
• Filed: 06/20/2018
• Issued: 06/18/2019
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Ngan, Ricky Yik Hei, Zahirovic, Nino, Azizi, Yaser
• Primary Examiner(s): Lee, Nicholas J
• Application Number:
  US16/013,005
• Publication Number:
  US 20180301072A1
• Time in Patent Office: 363 Days
• Field of Search: None
• CPC Class Codes: G09G 2230/00 Details of flat display driving waveforms
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A system reads a desired circuit parameter from a pixel circuit that includes a light emitting device, a drive device to provide a programmable drive current to the light emitting device, a programming input, and a storage device to store a programming signal. One embodiment of the extraction system turns off the drive device and supplies a predetermined voltage from an external source to the light emitting device, discharges the light emitting device until the light emitting device turns off, and then reads the voltage on the light emitting device while that device is turned off. The voltages on the light emitting devices in a plurality of pixel circuits may be read via the same external line, at different times.

Claims

1. A display comprising:

a first signal line for supplying a programming voltage;

a second signal line for outputting an output voltage or current value which is a function of a parameter of at least one of the pixel circuits;

a plurality of pixel circuits, each pixel circuit comprising;

a light emitting device;

a drive transistor, controllably coupling an electrical power source to the light emitting device for supplying a controllable electrical current to the light emitting device, said drive transistor having a gate terminal, a source terminal and a drain terminal;

a first switching transistor controllably coupling the first signal line to the gate terminal of the drive transistor at a first node;

a second switching transistor controllably coupling the second signal line to one of the source and drain terminals of the drive transistor at a second node;

a storage device coupled between the first node and the second node; and

a controller coupled to each pixel circuit and configured to supply controlling input signals to the first and second switching transistors in a predetermined sequence to produce the output voltage or current value which is a function of a parameter of the pixel circuit, the sequence including;

i) turning on at least one of the first and second switching transistors to supply first and second initial voltages to the first and second nodes, respectively;

ii) turning off the second switching transistor, and connecting the electrical power source to the drive transistor so that current flows from the electrical power source to the light emitting device through the drive transistor, the magnitude of said current being controlled by the voltage applied to the gate terminal of the drive transistor discharged by the storage device; and

iii) turning on the second switching transistor and extracting a parameter of the drive transistor by reading the voltage at the second node.

2. The display according to claim 1, wherein the controller is configured to extract the parameter after the light emitting device turns off;

wherein the voltage is a function of the threshold voltage of the light emitting device.

3. The display according to claim 1, wherein the controller is configured to extract the parameter after the drive transistor turns off;

wherein the voltage is a function of the threshold voltage of the drive transistor.

4. The display according to claim 1, wherein the controller is configured to supply the initialize voltage to the first and second nodes externally via the second line.

5. The display according to claim 1, wherein the controller is configured to supply the initial voltage to the first node via the first line, and supplying the initial voltage to the second node via the second line.

6. The display according to claim 1, wherein the controller is configured to supply controlling input signals to the first and second switching transistors to turn off both the first and second switching transistors to reset the voltages at the first and second nodes.

7. The display according to claim 1, further comprising a third switching transistor controllably coupling said power source to the drive transistor that is coupled to the second switching transistor;

wherein the second node is between the third switching transistor and the drive transistor; and

wherein the controller is configured to delay connecting the electric power source to the drive transistor in step ii) using the third switching transistor.

8. The display according to claim 1, wherein the controller is configured to:

turn on the drive device and measure the current and voltage of the drive transistor while changing the voltage between the gate and the source or drain of the drive transistor to operate the drive transistor in the linear regime during one time interval and in the saturated regime during a second time interval, and

extract the voltage of the light emitting device from the relationship of the currents and voltages measured with the drive transistor operating in the two regimes.

9. The display according to claim 1, wherein the controller is configured to turn off the drive transistor during step ii);

and

extract an off voltage of the light emitting device when the light emitting device turns off during step iii).

10. The display according to claim 1, wherein the controller is configured to determine a parasitic capacitance by:

determining a first voltage or current on the second node during step i);

determining a second voltage or current on the second node during step iii); and

based on a pixel model, calculate the parasitic capacitance from the first and second voltages or currents.

11. A method of operating a display to produce an output voltage or current value which is a function of a parameter of the pixel circuit, the display comprising:

a first signal line for supplying a programming voltage;

a second signal line for outputting an output voltage or current value which is a function of a parameter of at least one of the pixel circuits;

a plurality of pixel circuits, each pixel circuit comprising;

a light emitting device;

a drive transistor, controllably coupling an electrical power source to the light emitting device for supplying a controllable electrical current to the light emitting device, said drive transistor having a gate terminal, a source terminal and a drain terminal;

a first switching transistor controllably coupling the first signal line to the gate terminal of the drive transistor at a first node;

a second switching transistor controllably coupling the second signal line to one of the source and drain terminals of the drive transistor at a second node;

a storage device coupled between the first node and the second node; and

a controller coupled to each pixel circuit and capable of supplying controlling input signals to the first and second switching transistors in a predetermined sequence to produce the output voltage or current value which is a function of the parameter of the pixel circuit,

the method comprising;

i) turning on at least one of the first and second switching transistors to supply first and second initial voltage to the first and second nodes, respectively;

ii) turning off the second switching transistor, and connecting the electrical power source to the drive transistor so that current flows from the electrical power source to the light emitting device through the drive transistor, the magnitude of said current being controlled by the voltage applied to the gate terminal of the drive transistor discharged by the storage device; and

iii) turning on the second switching transistor and extracting the parameter of the drive transistor by reading the voltage at the second node.

12. The method according to claim 11, wherein step iii) includes extracting the parameter after the light emitting device turns off;

wherein the voltage is a function of the threshold voltage of the light emitting device.

13. The method according to claim 11, wherein step iii) includes extracting the parameter after the drive transistor turns off;

wherein the voltage is a function of the threshold voltage of the drive transistor.

14. The method according to claim 11, wherein step i) includes supplying the initialize voltage to the first and second nodes externally via the second line.

15. The method according to claim 11, wherein step i) includes supplying the initial voltage to the first node via the first line, and supplying the initial voltage to the second node via the second line.

16. The method according to claim 11, further comprising supplying controlling input signals to the first and second switching transistors to turn off both the first and second switching transistors to reset the voltages at the first and second nodes.

17. The method according to claim 11, wherein each pixel further comprises a third switching transistor controllably coupling said power source to the drive transistor that is coupled to the second switching transistor;

wherein the second node is between the third switching transistor and the drive transistor; and

wherein the controller is capable of delaying connecting the electric power source to the drive transistor in step ii) using the third switching transistor.

18. The method according to claim 11, wherein step iii) includes turning on the drive device and measuring the current and voltage of the drive transistor while changing the voltage between the gate and the source or drain of the drive transistor to operate the drive transistor in the linear regime during one time interval and in the saturated regime during a second time interval, and

extracting the voltage of the light emitting device from the relationship of the currents and voltages measured with the drive transistor operating in the two regimes.

19. The method according to claim 11, further comprising:

turning off the drive transistor during step ii); and

extracting an off voltage of the light emitting device when the light emitting device turns off during step iii).

20. The method according to claim 11, wherein step iii) includes determining a parasitic capacitance by:

determining a first voltage or current on the second node during step i);

determining a second voltage or current on the second node during step iii); and

based on a pixel model, calculate the parasitic capacitance from the first and second voltages or currents.