Method and device for removing self-interference signal in environment using FDR mode

• US 10,326,483 B2
• Filed: 10/21/2015
• Issued: 06/18/2019
• Est. Priority Date: 01/23/2015
• Status: Active Grant

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Dongkyu, Ko, Hyunsoo, Chung, Jaehoon, Choi, Kukheon, Noh, Kwangseok, Lee, Sangrim
• Primary Examiner(s): Akinyemi, Ajibola A
• Application Number:
  US15/545,515
• Publication Number:
  US 20180013466A1
• Time in Patent Office: 1,336 Days
• Field of Search: 455 78
• CPC Class Codes: H04B 1/12 Neutralising, balancing, or compensation arrangements
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/345 Interference values signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR] H04B17/336
• CPC Class Codes: H04B 7/0857 using maximum ratio combining techniques, e.g. signal-to- interference ratio [SIR], received signal strenght indication [RSS]
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 1/12 by using return channel
• CPC Class Codes: H04L 5/0044 allocation of payload
• CPC Class Codes: H04L 5/0055 Physical resource allocation for ACK/NACK for physical mapping arrangements in ARQ protocols H04L1/1861
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits

Abstract

A method for removing a self-interference signal by a device supporting an FDR mode can further comprise the steps of: transmitting a signal to a counterpart node in a predetermined time interval; generating, in an RF stage of the device, a residual self-interference signal after removal of an analog self-interference signal with respect to the signal and then storing same; and receiving from the counterpart node a NACK signal with respect to the transmission of the signal; retransmitting the signal to the counterpart node; and, if decoding of the signal which has been received in the predetermined time interval is successful, using only a part of the stored residual self-interference signal when removing a digital self-interference signal on the basis of the retransmission.

Claims

1. A method for performing self-interference signal cancellation by an apparatus operating in a full duplex communication (FDR) mode, the method comprising:

transmitting a signal to a target node in a predetermined time duration;

generating and storing a digital self-interference signal after analog self-interference signal cancellation with respect to the transmitted signal at a radio frequency (RF) end of the apparatus;

receiving a negative-acknowledgement (NACK) signal from the target node in response to the transmitted signal;

retransmitting the signal to the target node;

when a desired signal received in the predetermined time duration from the target node is not successfully decoded and the self-interference signal cancellation is successful, using a portion of the stored digital self-interference signal for the self-interference signal cancellation for the retransmitted signal; and

when the desired signal received in the predetermined time duration from the target node is not successfully decoded and the self-interference signal cancellation is not successful, reusing the stored digital self-interference signal for the self-interference signal cancellation for the retransmitted signal,

wherein the portion of the stored digital self-interference signal corresponds to components up to a predetermined order of the components of the stored digital self-interference signal.

2. The method of claim 1, further comprising:

obtaining other portions except the portion of the stored digital self-interference signal through self-interference signal estimation for the retransmitted signal.

3. The method of claim 1, wherein the components up to predefined order of the components of the stored digital self-interference signal include linear components and non-linear components of orders equal to or lower than the predetermined order of the stored digital self-interference signal.

4. The method of claim 3, further comprising:

obtaining non-linear components of orders higher than the predetermined order through self-interference signal estimation for the retransmitted signal.

5. The method of claim 1, wherein the predetermined order is determined based on transmit power of the transmitted signal.

6. An apparatus for performing self-interference signal cancellation, the apparatus supporting a full duplex communication (FDR) mode, the apparatus comprising:

a processor;

a transmitter configured to transmit a signal to a target node in a predetermined time duration;

a radio frequency (RF) chain configured to generate and store a digital self-interference signal after an analog self-interference signal cancellation with respect to the transmitted signal at an RF chain of the apparatus; and

a receiver configured to receive a negative-acknowledgement (NACK) signal from the target node in response to the transmitted signal,

wherein the transmitter is configured to retransmit the signal to the target node,

wherein, when a desired signal received in the predetermined time duration from the target node is not successfully decoded and the self-interference signal cancellation is successful, the processor is configured to use a portion of the stored digital self-interference signal for the self-interference signal cancellation for the retransmitted signal;

when the desired signal received in the predetermined time duration from the target node is not successfully decoded and the self-interference signal cancellation is not successful, the processor is configured to reuse the stored digital self-interference signal for the self-interference signal cancellation for the retransmitted signal, and

wherein the portion of the stored digital self-interference signal corresponds to components up to a predetermined order of the components of the stored digital self-interference signal.

7. The apparatus of claim 6, further comprising:

a processor configured to obtain other portions except the portion of the stored digital self-interference signal through self-interference signal estimation for the retransmitted signal.

8. The apparatus of claim 6, wherein the components up to predefined order of the components of the stored digital self-interference signal include linear components and non-linear components of orders equal to or lower than the predetermined order of the stored digital self-interference signal.

9. The apparatus of claim 8,

wherein the processor is configured to obtain non-linear components of orders higher than the predetermined order through self-interference signal estimation for the retransmitted signal.

10. The apparatus of claim 8, further comprising:

a processor configured to determine the predetermined order based on transmit power of the transmitted signal.