Wear-out monitor device

• US 10,338,132 B2
• Filed: 10/12/2016
• Issued: 07/02/2019
• Est. Priority Date: 04/19/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices, Inc.
• Inventors: Coyne, Edward John, O'Donnell, Alan J., Heffernan, Colm Patrick, Manning, Kevin B., Forde, Mark, Clarke, David J., O'Dwyer, Thomas G., Aherne, David, Looby, Michael A.
• Primary Examiner(s): Hoque, Farhana A
• Application Number:
  US15/291,742
• Publication Number:
  US 20170299649A1
• Time in Patent Office: 993 Days
• Field of Search: 32476201, 438 14
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

Claims

1. An integrated circuit device with wear out monitoring, the integrated circuit device comprising:

a core circuit;

a wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated; and

a sensing circuit configured to detect an electrical property associated with the wear-out monitor device, wherein the electrical property is indicative of the wear out of the core circuit,

wherein the wear-out monitor device comprises a substrate and monitor atoms configured to diffuse in the substrate, wherein a doping profile of the monitor atoms in the substrate is indicative of wear out of the core circuit.

2. The integrated circuit device of claim 1, wherein the monitor atoms have a diffusion activation energy between 0.75 eV and 2.5 eV in the substrate.

3. The integrated circuit device of claim 1, wherein the monitor atoms include one or more elements selected from the group consisting of aluminum (Al), cobalt (Co), platinum (Pt), sulfur (S), nickel (Ni), silver (Ag), zinc (Zn), gold (Au), chromium (Cr), copper (Cu), iron (Fe), sodium (Na), and potassium (K).

4. The integrated circuit device of claim 1, wherein the core circuit and the wear-out monitor device are formed in the substrate that is a common substrate formed of a semiconductor material and configured such that the monitor atoms remain in the wear-out monitor device under a wear-out stress without diffusing into the core circuit.

5. The integrated circuit device of claim 1, wherein the wear-out monitor device comprises a reservoir of the monitor atoms formed on a surface of the substrate, wherein the reservoir serves as a first electrode of the wear-out monitor device, and wherein the wear-out monitor device further comprises a second electrode on the surface formed of a different material than the first electrode.

6. The integrated circuit device of claim 5, wherein the substrate comprises a semiconductor material as a diffusing medium for the monitor atoms.

7. The integrated circuit device of claim 6, wherein the monitor device comprises a PN junction, wherein the reservoir physically contacts one of a p-doped region or an n-doped region of the PN junction, and wherein the second electrode electrically contacts the other of the p-doped region or the n-doped region.

8. The integrated circuit device of claim 7, wherein the electrical property includes a reverse bias current of the PN junction.

9. The integrated circuit device of claim 6, wherein the monitor device comprises a first doped region and a second doped region that are separated from each other and configured to punch-through under a bias between the first doped region and the second doped region, wherein the first doped region and the second doped region have opposite conductivity types, and wherein the monitor atoms are configured to diffuse from the first doped region towards the second doped region under the bias.

10. The integrated circuit device of claim 9, wherein the second doped region is a buried region that is vertically separated from the first doped region that is formed at a surface of the semiconductor material.

11. The integrated circuit device of claim 9, wherein the first doped region and the second doped region are formed at a surface region of the semiconductor material and are laterally separated from each other.

12. The integrated circuit device of claim 6, wherein the monitor device comprises a field effect transistor comprising a source region and a drain region that are separated from each other by a channel region, and wherein, under a bias, the monitor atoms are configured to diffuse from one of the source region or the drain region into the channel towards the other of the source region or the drain region.

13. The integrated circuit device of claim 6, further comprising a reference device coupled to the sensing circuit, wherein the sensing circuit is configured to provide an indication of wear-out based on a comparison of the electrical property of the wear-out monitor device with a corresponding electrical property of the reference device.

14. The integrated circuit device of claim 13, wherein the reference device comprises the same type of device as the wear-out monitor device while having at least one electrode formed of a material different than a corresponding electrode of the wear-out monitor device having the monitor atoms.

15. The integrated circuit device of claim 1, wherein the monitor atoms are configured such that a wear-out stress causes a change in a rate at which the monitor atoms diffuse in the substrate.

16. The integrated circuit device of claim 1, wherein the wear-out monitor device comprises a p-doped region and an n-doped region, wherein the p-doped region comprises a p-type dopant different from the monitor atoms and the n-doped region comprises an n-type dopant different from the monitor atoms.

17. The integrated circuit device of claim 1, wherein the indication of wear-out is indicative of one or more of a thermal stress, a voltage stress, or a current stress.

18. The integrated circuit device of claim 1, wherein the indication of wear out is based on diffusion of monitor atoms in the wear-out monitor device.

19. The integrated circuit device of claim 1, wherein the wear-out monitor device and the core circuit are integrated in a common substrate.

20. The integrated circuit device of claim 1, wherein the substrate comprises a semiconductor substrate.

21. The integrated circuit device of claim 1, wherein the substrate comprises an insulating substrate.

22. A method of monitoring a wear-out of an integrated circuit device comprising a core circuit and a wear-out monitor device, the method comprising:

detecting an electrical property of a wear-out monitor device, wherein the wear-out monitor device comprises a semiconductor material and monitor atoms configured to diffuse into the semiconductor material, and wherein the electrical property corresponds to a concentration profile of the monitor atoms in the semiconductor material that is indicative of wear-out of the core circuit; and

reporting the electrical property of the wear-out monitor device.

23. The method of claim 22, wherein, prior to detecting, subjecting the integrated circuit device to a stress condition that causes the monitor atoms to diffuse in the semiconductor material.

24. The method of claim 23, wherein the monitor device comprises a plurality of doped regions and a reservoir of the monitor atoms physically contacting one of the doped regions and serving as an electrode, and wherein detecting the electrical property comprises measuring a current or a voltage using the electrode.

25. The method of claim 23, wherein the stress condition comprises one or more of a thermal stress condition, a voltage stress condition, or a current stress condition.

26. The method of claim 22, further comprising determining whether the wear-out of the core circuit has reached a predetermined level based on the detected electrical property of the wear-out device.

27. The method of claim 22, wherein the monitor atoms have a diffusion activation energy between 0.75 eV and 2.5 eV in the semiconductor material.

28. The method of claim 22, wherein the wear-out monitor device and the core circuit are integrated in a common substrate.

29. An integrated circuit device with wear-out monitoring, the integrated circuit device comprising:

a core circuit;

means for recording wear-out of the core circuit as a doping profile of a diffusing material in a substrate wherein the doping profile is indicative of wear out of the core circuit; and

means for detecting an indication of wear-out of the core circuit, the means for recording wear-out being in communication with the means for recording the indication of wear-out.

30. The integrated circuit device of claim 29, wherein the diffusing material has a diffusion activation energy in the substrate between 0.75 eV and 2.5 eV.

31. The integrated circuit device of claim 29, wherein the diffusing material include one or more elements selected from the group consisting of aluminum (Al), cobalt (Co), platinum (Pt), sulfur (S), nickel (Ni), silver (Ag), zinc (Zn), gold (Au), chromium (Cr), copper (Cu), iron (Fe), sodium (Na), and potassium (K).

32. The integrated circuit device of claim 29, wherein the substrate comprises a semiconductor substrate.

33. The integrated circuit device of claim 29, wherein the means for recording wear-out and the core circuit are integrated in a common substrate.