Extracting debug information from FPGAs in multi-tenant environments

• US 10,338,135 B2
• Filed: 09/28/2016
• Issued: 07/02/2019
• Est. Priority Date: 09/28/2016
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Davis, Mark Bradley, Pettey, Christopher Joseph, Khan, Asif, Atta, Islam Mohamed Hatem Abdulfattah Mohamed
• Primary Examiner(s): Abraham, Esaw T
• Application Number:
  US15/279,276
• Publication Number:
  US 20180088174A1
• Time in Patent Office: 1,007 Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Claims

1. A system, comprising:

a host computing device executing two or more user partitions at a first privilege level and executing a privileged host partition at a second privilege level greater than the first privilege level, wherein the first privilege level allows access to at least one of the two or more user partitions and restricts access to the privileged host partition, and the second privilege level allows access to the privileged host partition; and

a reconfigurable logic device having reconfigurable logic programmed to include two or more application logic units, each of the application logic units associated with one of the user partitions and being configured to communicate debug data generated by operating the application logic unit via a different communication lane to the associated user partition.

2. The system of claim 1, wherein the reconfigurable logic device further comprises host logic to supervise operation of the application logic units, the host logic being controlled by the host partition.

3. The system of claim 2, wherein the application logic units communicate to the host computing device via a network interface not supervised by the host logic.

4. The system of claim 2, wherein the application logic units communicate to the host computing device via an independent communication channel provided by the host logic.

5. The system of claim 2, wherein, the host logic transmits debug data for two or more of the application logic units via a supervisor privilege communication channel.

6. The system of claim 2, wherein at least one of the application logic units further comprises a logic analyzer configured to generate signal values of the debug data by sampling logic signals within the at least one application logic unit.

7. The system of claim 2, wherein, the host logic allows debug data generated by one of the application logic units from being accessed by other user partitions on the host computing device.

8. The system of claim 1, wherein each of the user partitions executes in a different virtual machine of the host computing device.

9. The system of claim 1, wherein the debug data includes one or more of the following:

signal values, values stored in a memory in the reconfigurable logic device, values stored in a memory coupled to the reconfigurable logic device, event counter values, or trigger values.

10. The system of claim 1, wherein the debug data are generated by one or more of the following components configured in the reconfigurable logic device:

logic probes coupled to capture values generated by accelerator logic, logic probes that capture values generated by accelerator logic with use of a trigger, event counters, energy counters, scan out values, or interrupts generated by setting breakpoints, embedded FPGA memories, or memory devices coupled to the reconfigurable logic device.

11. The system of claim 1, wherein the reconfigurable device further comprises circuitry configured to modify signal values in the application logic unit with one or more of the following components:

a scan cell input, forcing a state element value, resetting or setting an event counter to a prescribed value, or setting an interrupt breakpoint.

12. A method, comprising:

with a host computing device, executing a privileged host partition at a first privilege level and one or more user partitions at a second privilege level less than the first privilege level, wherein the first privilege level allows access to the privileged host partition, and the second privilege level allows access to at least one of the one or more user partitions and restricts access to the privileged host partition; and

with a reconfigurable logic device having reconfigurable logic programmed to include one or more application logic units, communicating debug data generated by operating one of the application logic units via an assigned communication lane to an assigned user partition of the user partitions.

13. The method of claim 12, further comprising supervising the application logic units with host logic programmed on the reconfigurable logic device, the host logic being controlled by the host partition.

14. The method of claim 13, further comprising, with the application logic units, communicating to the host computing device via a network interface not supervised by the host logic.

15. The method of claim 13, further comprising, with the application logic units, communicating to the host computing device via an independent communication channel provided by the host logic.

16. The method of claim 13, further comprising, with the host logic, transmitting debug data for two or more of the application logic units via a supervisor privilege communication channel.

17. The method of claim 13, further comprising, with a logic analyzer configured in the application logic units, generating signal values of the debug data by sampling logic signals within the at least one application logic unit.

18. The method of claim 13, further comprising, by the host logic, preventing debug data generated by one of the application logic units from being accessed by other user partitions on the host computing device.

19. The method of claim 12, wherein each of the user partitions executes in a different virtual machine of the host computing device.

20. The method of claim 12, wherein the debug data includes one or more of the following:

signal values, values stored in a memory in the reconfigurable logic device, values stored in a memory coupled to the reconfigurable logic device, event counter values, or trigger values.

21. The method of claim 12, wherein the debug data are generated by one or more of the following components configured in the reconfigurable logic device:

logic probes coupled to capture values generated by accelerator logic, logic probes that capture values generated by accelerator logic with use of a trigger, event counters, energy counters, scan out values, or interrupts generated by setting breakpoints, embedded FPGA memories, or memory devices coupled to the reconfigurable logic device.

22. The method of claim 12, wherein the reconfigurable device further comprises circuitry configured to modify signal values in the application logic unit with one or more of the following components:

a scan cell input, forcing a state element value, resetting or setting an event counter to a prescribed value, or setting an interrupt breakpoint.

23. One or more computer-readable storage devices or memory storing configuration data for programming a configuration memory in a field programmable gate array (FPGA) coupled to a host computing device executing a privileged host partition and one or more user partitions, the privileged host partition executing at a greater level of privilege than the user partitions, wherein the greater level of privilege allows access to the privileged host partition and the user partitions are restricted from accessing the privileged host partition, the FPGA when so programmed performing a method, the method comprising:

with one or more application logic units programmed in the FPGA, communicating debug data generated by operating one of the application logic units via an assigned communication lane to a different one of the user partitions executing on the host computing device.

24. The computer-readable storage devices or memory of claim 23, wherein the method further comprises supervising operation of the application logic units with host logic programmed on the reconfigurable logic device, the host logic being controlled by the host partition.

25. The computer-readable storage devices or memory of claim 23, wherein the configuration data further comprises data for configuring a logic analyzer in at least one of the application logic units, the logic analyzer generating signal values of the debug data by sampling logic signals within the at least one application logic unit.

26. The computer-readable storage devices or memory of claim 23, wherein the configuration data further comprises host logic preventing debug data generated by one of the application logic units from being accessed by other user partitions on the host computing device.

27. The computer-readable storage devices or memory of claim 23, wherein the debug data are generated by one or more of the following components configured in the reconfigurable logic device:

logic probes coupled to capture values generated by accelerator logic, logic probes that capture values generated by accelerator logic with use of a trigger, event counters, energy counters, scan out values, or interrupts generated by setting breakpoints, embedded FPGA memories, or memory devices coupled to the reconfigurable logic device.