Switch having first and second switching elements connected in parallel with one another

• US 10,347,623 B2
• Filed: 05/02/2017
• Issued: 07/09/2019
• Est. Priority Date: 05/03/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bakalski, Winfried
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/584,467
• Publication Number:
  US 20170323881A1
• Time in Patent Office: 798 Days
• Field of Search: 327436
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 17/284 in field effect transistor switches
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load

Abstract

A switch includes an input terminal and an output terminal. The switch also includes a first stack having transistors coupled in series, and a second stack having transistors coupled in series. The first stack and the second stack are connected in parallel with one another.

Claims

1. A switch, comprising:

an input terminal;

an output terminal

a first stack comprising transistors coupled in series, the first stack being coupled between the input terminal and the output terminal; and

a second stack comprising transistors coupled in series, the second stack being coupled between the input terminal and the output terminal,

wherein the first stack and the second stack are connected in parallel with one another,

wherein the transistors of the first stack have first time constants,

wherein the transistors of the second stack have second time constants,

wherein at least some of the second time constants have larger values than the first time constants,

wherein the second time constants assume different values for different transistors of the second stack, and

wherein a time constant of a transistor of the second stack that is adjacent to the input terminal assumes the largest value of all the second time constants.

2. The switch of claim 1, wherein a smallest value of the second time constants is greater than a largest value of the first time constants at least by a factor of five.

3. The switch of claim 1,

wherein the first time constants have values of less than 50 μ

s, and/or

wherein the second time constants have values of greater than 50 μ

s.

4. The switch of claim 1,

wherein the second stack comprises, for each transistor of the first stack, an associated transistor,

wherein a source contact of each transistor of the second stack is coupled to a source contact of the respectively associated transistor of the first stack,

wherein a drain contact of each transistor of the second stack is coupled to a drain contact of the respectively associated transistor of the first stack.

5. The switch of claim 1, further comprising:

a control terminal configured to receive a control signal and which is coupled to gate contacts of the transistors of the first stack in order to operate the transistors of the first stack in a non-conducting state or a conducting state depending on the control signal.

6. The switch of claim 5, wherein the control terminal is not configured to operate the transistors of the second stack in the non-conducting state or in the conducting state depending on the control signal.

7. The switch of claim 1, further comprising:

a voltage source configured to generate a bias voltage signal and which is coupled to gate contacts of the transistors of the second stack, wherein the voltage source is configured to operate the transistors of the second stack in a non-conducting state by means of the bias voltage signal.

8. The switch of claim 7, wherein the voltage source is not configured to operate the transistors of the first stack in the non-conducting state or in the conducting state by means of the bias voltage signal.

9. The switch of claim 7,

wherein the voltage source is coupled to the gate contacts of the transistors of the second stack via gate contact resistors,

wherein the gate contact resistors have identical values for different field effect transistors of the second stack.

10. The switch of claim 7,

wherein the voltage source is coupled to the gate contacts of the transistors of the second stack via gate contact resistors,

wherein the gate contact resistors have different values for different transistors of the second stack.

11. The switch of claim 10, wherein the gate contact resistor of the transistor of the second stack that is adjacent to the input terminal has the largest value in comparison with the gate contact resistors of the transistors of the second stack that are not adjacent to the input terminal.

12. The switch of claim 10, wherein the gate contact resistors of the transistors of the second stack have values that decrease continuously beginning from the transistor adjacent to the input terminal through to the transistor adjacent to the output terminal.

13. The switch of claim 9, wherein at least the gate contact resistor of the transistor adjacent to the input terminal has a value of greater than 100 kohms.

14. The switch of claim 1,

wherein a variation of gate widths and/or of gate lengths of the transistors of the first stack is not greater than 20%,

wherein a variation of gate widths and/or of gate lengths of the transistors of the second stack is not greater than 20%.

15. A system, comprising:

a switch comprising an input terminal, an output terminal, a first stack comprising transistors coupled in series, the first stack being coupled between the input terminal and the output terminal, and a second stack comprising transistors coupled in series, the second stack being coupled between the input terminal and the output terminal, wherein the first stack and the second stack are connected in parallel with one another;

an LC resonant circuit coupled to the input terminal of the switch; and

a ground contact coupled to the output terminal of the switch,

wherein the transistors of the first stack have first time constants,

wherein the transistors of the second stack have second time constants,

wherein at least some of the second time constants have larger values than the first time constants,

wherein the second time constants assume different values for different transistors of the second stack, and

wherein a time constant of a transistor of the second stack that is adjacent to the input terminal assumes the largest value of all the second time constants.

16. A switch, comprising:

an input terminal;

an output terminal;

a first switching element coupled between the input terminal and the output terminal;

a second switching element coupled between the input terminal and the output terminal;

wherein the first switching element and the second switching element are connected in parallel with one another,

wherein the first switching element has a first time constant,

wherein the first switching element has with a second time constant,

wherein the first and second time constants are time measurements of how fast the transistors can be switched,

wherein the second time constant is greater than the first time constant,

wherein the first switching element comprises a first stack comprising transistors coupled in series,

wherein the second switching element comprises a second stack comprising transistors coupled in series,

wherein the transistors of the first stack have first time constants,

wherein the transistors of the second stack have second time constants,

wherein at least some of the second time constants have larger values than the first time constants,

wherein the second time constants assume different values for different transistors of the second stack, and

wherein a time constant of a transistor of the second stack that is adjacent to the input terminal assumes the largest value of all the second time constants.