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Configurable wireless charging transmit and receive monitoring device

  • US 10,348,139 B2
  • Filed: 09/29/2017
  • Issued: 07/09/2019
  • Est. Priority Date: 09/29/2017
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • N shared input/output (I/O) connections, each of the N shared I/O connections being configured to connect to N respective coils, wherein N is a positive integer greater than 1;

    an analog multiplexer having N mux inputs each connected to a respective one of the N shared I/O connections, the analog multiplexer configured to direct an AC input signal from a selected one of the N mux inputs to a mux output when the analog multiplexer is enabled;

    a receiver circuit configured to receive the AC input signal and convert the AC input signal to a digital signal;

    a digital signal processor (DSP) configured to process the digital signal in accordance with a predetermined configuration and output processed data;

    a pulse width modulation (PWM) generator configured to output PWM signals in accordance with a PWM control signal;

    N gate drivers connected such that each respective gate driver receives a PWM signal from the PWM generator and a respective gate driver enable signal, each gate driver being configured to transmit an AC signal relative to the PWM signal only when enabled by the respective gate driver enable signal, the AC signal being provided to the respective one of the N shared I/O connections;

    a control portion configured to provide mux enable and mux select signals to the analog multiplexer and to provide respective gate driver enable signals to respective N gate drivers in accordance with the predetermined configuration, such that when the analog multiplexer is not enabled by the mux enable signal, any of the N gate drivers can be enabled by the respective gate driver enable signal, and such that when the analog multiplexer is enabled by the mux enable signal and the mux select signal designates the selected one of the N mux inputs then any of the N gate drivers can be enabled by the respective gate driver enable signal except for one of the N gate drivers that is respective to the selected one of the N mux inputs.

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