FinFETs having strained channels, and methods of fabricating finFETs having strained channels

• US 10,355,020 B2
• Filed: 06/13/2016
• Issued: 07/16/2019
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Qing, Cai, Xiuyu, Xie, Ruilong, Yeh, Chun-chen
• Primary Examiner(s): Nguyen, Sophia T
• Application Number:
  US15/180,860
• Publication Number:
  US 20160293761A1
• Time in Patent Office: 1,128 Days
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G10L 15/16 using artificial neural networks
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 : the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/13067 : FinFET, source/drain region shapes fins on the silicon surface

Abstract

Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Claims

1. A finFET comprising:

a fin having a recessed source region located on one side of a non-recessed region and a recessed drain region located on another side of the non-recessed region, the recessed source and drain regions having a height that is less than a height of the non-recessed region;

a spacer layer comprising a recessed spacer layer portion located laterally adjacent to, and entirely along, sidewalls of the recessed source and drain regions, and a gate spacer layer portion along sidewalls of a gate structure of the finFET;

a strain-inducing material having a bottommost surface that is located entirely on a topmost surface of the recessed source and drain regions, wherein the topmost surface of the recessed source and drain regions is coplanar with a recessed surface of the recessed spacer layer portion that is adjacent to the sidewalls of the recessed source and drain regions; and

an insulating layer comprising a first portion located between the recessed source and drain regions and the recessed spacer layer portion, and beneath a bottommost surface of the recessed spacer layer portion, and a second portion located on the non-recessed region of the fin and beneath a gate portion of the overlying gate structure, wherein the first portion of the insulating layer has a recessed surface that is coplanar with the recessed surface of the recessed spacer layer portion and the topmost surface of the recessed source and drain regions, and wherein the first portion of the insulating layer and the recessed spacer layer portion are both U-shaped, and the second portion of the insulating layer has a sidewall that directly contacts a first portion of a sidewall of the strain-inducing material.

2. The finFET of claim 1, wherein a width of the fin is between approximately 3 nm and approximately 10 nm.

3. The finFET of claim 1, wherein the strain-inducing material comprises epitaxially-grown material.

4. The finFET of claim 1, wherein the strain-inducing material is configured to impart strain to a channel region of the finFET.

5. The finFET of claim 1, wherein a lattice parameter of the strain-inducing material differs from a lattice parameter of the fin.

6. The finFET of claim 1, wherein the spacer layer comprises one or more nitrides.

7. The finFET of claim 1, wherein the finFET is formed on a silicon-on-insulator (SOI) substrate.

8. The finFET of claim 7, wherein the finFET is formed on a buried oxide (BOX) layer of the SOI substrate.

9. The finFET of claim 1, wherein the second portion of the insulating layer extends beneath, and is in direct physically contact with, a bottommost surface of the gate spacer layer.

10. The finFET of claim 1, wherein a lower portion of the gate spacer layer directly contacts a second portion of the sidewall of the strain-inducing material.