Single-curvature cavity for semiconductor epitaxy

• US 10,355,104 B2
• Filed: 10/27/2017
• Issued: 07/16/2019
• Est. Priority Date: 10/27/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Qi, Yi, Lim, Sang Woo, Koo, Kyung-Bum, Vinslava, Alina, Zhao, Pei, Hu, Zhenyu, Lo, Hsien-Ching, Shepard, Jr., Joseph F., Pandey, Shesh Mani
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US15/795,833
• Publication Number:
  US 20190131432A1
• Time in Patent Office: 627 Days
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

Claims

1. A method for forming a field-effect transistor, the method comprising:

forming a gate structure that overlaps with a channel region beneath a top surface of a semiconductor fin;

etching the semiconductor fin with an anisotropic etching process to form a cavity having a sidewall with a curved section and a planar section arranged between the curved section and the top surface of the semiconductor fin, wherein the planar section is located adjacent to the channel region in the semiconductor fin; and

etching the semiconductor fin with a conformally isotropic etching process having approximately equal horizontal and vertical etch rates that expands a volume of the cavity without changing an aspect ratio of the cavity and without changing a shape of the curved section and the planar section of the sidewall.

2. The method of claim 1 wherein the planar section intersects the top surface at a right angle.

3. The method of claim 1 further comprising:

epitaxially growing an embedded source/drain region in the cavity.

4. The method of claim 3 wherein the embedded source/drain region includes internal stress that is transferred to the channel region in the semiconductor fin.

5. The method of claim 4 wherein the embedded source/drain region is composed of silicon-germanium, the field-effect transistor is a p-type field-effect transistor, and the embedded source/drain region transfers compressive strain to the channel region.

6. The method of claim 4 wherein the embedded source/drain region is composed of carbon-doped silicon, the field-effect transistor is an n-type field-effect transistor, and the embedded source/drain region transfers tensile strain to the channel region.

7. The method of claim 1 wherein the gate structure includes a gate electrode, and further comprising:

forming a sidewall spacer adjacent to the gate electrode,

wherein the planar section of the sidewall is arranged beneath the sidewall spacer.

8. The method of claim 7 wherein the anisotropic etching process is self-aligned by the sidewall spacer.

9. The method of claim 1 wherein the semiconductor fin is composed of silicon, and the anisotropic etching process is performed using a source gas containing a mixture of hydrogen bromide and chlorine.

10. The method of claim 1 wherein the semiconductor fin is composed of silicon, and the conformally isotropic etching process is performed using radicals generated from a first source gas containing a mixture of ammonia and hydrogen.

11. The method of claim 10 wherein the anisotropic etching process is performed using a second source gas containing a mixture of hydrogen bromide and chlorine.

12. The method of claim 1 wherein the planar section of the cavity is continuous with the curved section of the cavity following the conformally isotropic etching process.

13. The method of claim 1 wherein the cavity is isotropically expanded by the conformally isotropic etching process.

14. The method of claim 1 wherein the cavity has a shield shape following the conformally isotropic etching process.