High performance interconnect link layer

• US 10,360,098 B2
• Filed: 09/14/2016
• Issued: 07/23/2019
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willey, Jeff, Blankenship, Robert G., Swanson, Jeffrey C., Safranek, Robert J.
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US15/264,680
• Publication Number:
  US 20170123894A1
• Time in Patent Office: 1,042 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272

Abstract

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Claims

1. An apparatus comprising:

an exclusive OR (XOR) tree circuit to;

use a data mask to generate a sixteen bit cyclical redundancy check (CRC) value for at least a portion of a link layer flit; and

link layer logic implemented at least in part in hardware circuitry, wherein the link layer logic is to;

generate the link layer flit, wherein the link layer flit is generated to include a plurality of slots according to a format to enable a plurality of distinct messages to be packed into respective ones of the plurality of slots, wherein the portion of the flit comprises the plurality of slots, the flit is generated to include a sixteen bit CRC field separate from the plurality of slots and encoded with the CRC value, and the plurality of slots comprises at least three slots; and

transmitter hardware to send the flit to a receiver of another device on a data link, wherein the CRC value is to indicate whether an error is present on the data link.

2. The apparatus of claim 1, wherein the flit is included in at least a portion of a packet.

3. The apparatus of claim 1, wherein the flit comprises a 192 bit flit.

4. The apparatus of claim 1, wherein the first of the three slots comprises 72 bits, the second of the three slots comprises 70 bits, and third slot comprises 18 bits.

5. The apparatus of claim 4, wherein the data link comprises at least 8 lanes in a first state and the flit comprises 192 bits.

6. The apparatus of claim 5, wherein the first state comprises a partial width transmitting state and a full width transmitting state comprises a 20 lane link.

7. The apparatus of claim 3, wherein payload of the flit comprises 176 bits.

8. The apparatus of claim 1, wherein the XOR tree circuit implements a XOR tree based on a polynomial to generate the CRC value.

9. The apparatus of claim 8, wherein the polynomial comprises g(x)=(x¹⁶+x¹⁵+x¹³+x¹²+x¹⁰+x⁹+x⁸+x⁷+x⁶+x⁴+x³+x¹+1).

10. The apparatus of claim 1, wherein the link layer logic is further to invert the CRC value prior to sending the flit.

11. The apparatus of claim 1, wherein the CRC value comprises a rolling CRC value.

12. The apparatus of claim 11, wherein the rolling CRC value comprises a 32 bit rolling CRC value.

13. The apparatus of claim 1, wherein the data mask comprises a 176-bit data mask.

14. An apparatus comprising:

hardware circuitry to implement a protocol stack comprising a physical layer, a link layer, a routing layer, and a protocol layer, wherein the hardware circuitry comprises;

an exclusive OR (XOR) tree circuit to use a data mask to generate a 16-bit cyclical redundancy check (CRC) value for a 192-bit flit;

link layer logic implemented at least in part in hardware circuitry to generate the flit, wherein the link layer flit is generated to include a plurality of slots according to a format to enable a plurality of distinct messages to be packed into respective ones of the plurality of slots, the flit is generated to include the CRC value within a 16-bit CRC field, and the CRC field is separate from the plurality of slots and is to identify errors on a data link; and

physical layer circuitry to transfer information included in the flit on a physical medium.

15. The apparatus of claim 14, wherein the CRC value comprises a rolling CRC value.

16. The apparatus of claim 15, wherein the rolling CRC value comprises a 32 bit rolling CRC value.

17. The apparatus of claim 14, wherein the data mask comprises a 176-bit data mask.