Parallel use of integrated non-volatile memory and main volatile memory within a mobile device

• US 10,360,143 B2
• Filed: 07/01/2010
• Issued: 07/23/2019
• Est. Priority Date: 07/01/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chun, Christopher Kong Yee
• Primary Examiner(s): Grullon, Francisco A
• Application Number:
  US12/828,815
• Publication Number:
  US 20120004011A1
• Time in Patent Office: 3,309 Days
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A mobile device having parallel use of non-volatile memory and main memory is presented. The mobile device includes a volatile memory, a non-volatile memory, a memory controller functionally coupled to the non-volatile memory and the volatile memory, and a processor coupled to the memory controller. The processor addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map. Alternatively, a mobile device may include a volatile memory, a non-volatile memory, a memory controller coupled to the volatile memory, a processor coupled to the memory controller. The processor may address the volatile memory during normal operation. The mobile device may further include a shadow copy controller coupled to the non-volatile memory and the memory controller, where the shadow copy controller copies information stored in a designated portion of the volatile memory into the non-volatile memory.

Claims

1. A mobile device, comprising:

a volatile memory;

a non-volatile memory comprising a Magnetoresistive Random Access Memory (MRAM);

a memory controller functionally coupled to the non-volatile memory and the volatile memory; and

a processor coupled to the memory controller,

wherein the processor, during normal operation, addresses both the non-volatile memory and the volatile memory substantially at the same time utilizing a continuous memory map,

wherein the processor, during normal operation, writes system-state information to the non-volatile memory and/or reads the system-state information from the non-volatile memory,

wherein the processor, during normal operation, does not write the system-state information to the volatile memory, and

wherein normal operation refers to a state where the mobile device performs routine operations after a cold-boot or an instant on process.

2. The mobile device of claim 1, wherein the memory controller comprises:

a first memory controller coupled to the volatile memory; and

a second memory controller coupled to the non-volatile memory,

wherein the second memory controller allows the processor to address a section of the continuous memory map reserved for the non-volatile memory.

3. The mobile device of claim 1, wherein the non-volatile memory further comprises at least one of a Spin Transfer Torque MRAM (STT-MRAM) and a combination of the MRAM and STT-MRAM.

4. The mobile device of claim 1, wherein the processor writes instant-on information to the non-volatile memory and/or reads the instant-on information from the non-volatile memory.

5. The mobile device of claim 1, wherein the processor writes security information to the non-volatile memory and/or reads the security information from the non-volatile memory.

6. The mobile device of claim 1, wherein the processor writes digital rights management (DRM) information to the non-volatile memory and/or reads the DRM information from the non-volatile memory.

7. The mobile device of claim 1, wherein the volatile memory, the non-volatile memory, the memory controller and the processor are integrated into at least one semiconductor die.

8. A mobile device, comprising:

a volatile memory;

a non-volatile memory;

a memory controller functionally coupled to the non-volatile memory and the volatile memory; and

a processor coupled to the memory controller,

wherein the processor, during normal operation, addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map,

wherein the processor, during normal operation, writes system-state information to the non-volatile memory and/or reads the system-state information from the non-volatile memory,

wherein the processor, during normal operation, does not write the system-state information to the volatile memory, and

wherein normal operation refers to a state where the mobile device performs routine operations after a cold-boot or an instant on process.

9. The mobile device of claim 8, wherein the memory controller comprises:

a first memory controller coupled to the volatile memory; and

a second memory controller coupled to the non-volatile memory,

wherein the second memory controller allows the processor to address a section of the continuous memory map reserved for the non-volatile memory.

10. The mobile device of claim 8, wherein the non-volatile memory further comprises at least one of a Spin Transfer Torque MRAM (STT-MRAM) and a combination of a Magnetoresistive Random Access Memory (MRAM) and the STT-MRAM.

11. The mobile device of claim 8, wherein the processor writes instant-on information to the non-volatile memory and/or reads the instant-on information from the non-volatile memory.

12. The mobile device of claim 8, wherein the processor writes security information to the non-volatile memory and/or reads the security information from the non-volatile memory.

13. The mobile device of claim 8, wherein the processor writes digital rights management (DRM) information to the non-volatile memory and/or reads the DRM information from the non-volatile memory.

14. The mobile device of claim 8, wherein the volatile memory, the non-volatile memory, the memory controller and the processor are integrated into at least one semiconductor die.

15. The mobile device of claim 8, wherein the processor addresses both the non-volatile memory and the volatile memory substantially at the same time utilizing the continuous memory map.