Iterative soft information correction and decoding

• US 10,372,529 B2
• Filed: 12/17/2015
• Issued: 08/06/2019
• Est. Priority Date: 04/20/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Tai, Ying Yu, Jeon, Seungjune, Zhu, Jiangli
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US14/973,603
• Publication Number:
  US 20160306694A1
• Time in Patent Office: 1,328 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation

Abstract

A method is provided that includes performing first decoding operations on data obtained from a plurality of units of memory using soft information values for the plurality of units of memory, where the plurality of units of memory includes an error correction stripe. The method further includes determining that two or more units of memory have uncorrectable errors. The method further includes updating a soft information value for a first unit of memory in accordance with a magnitude of a soft information value for a second unit and a direction based on parity of the error correction stripe excluding the first unit, where the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors. The method further includes performing a second decoding operation on data obtained from the first unit using the updated soft information value.

Claims

1. A method performed by a storage device, the method comprising:

at the storage device;

receiving one or more read requests from a host system, the one or more read requests specifying data stored in a plurality of units of memory;

obtaining data from the plurality of units of memory in accordance with the one or more read requests;

performing first decoding operations on the data obtained from the plurality of units of memory using soft information values for the plurality of units of memory, wherein the plurality of units of memory includes an error correction stripe;

determining that two or more of the plurality of units of memory have uncorrectable errors, wherein the uncorrectable errors are uncorrectable using the first decoding operations;

updating a respective soft information value for a first unit of memory in accordance with;

a magnitude of a corresponding soft information value for a second unit of memory; and

a direction based on parity of the error correction stripe excluding the first unit of memory, wherein the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors;

performing a second decoding operation on data obtained from at least a portion of the first unit of memory using the updated soft information value;

in accordance with a determination that the second decoding operation is successful, providing decoded data from the second decoding operation to a memory controller; and

in accordance with a determination that the second decoding operation is unsuccessful, performing a set of remedial operations or providing an indication of an irresolvable error condition to a memory controller.

2. The method of claim 1, further including:

in accordance with the determination that the second decoding operation is successful, generating corrected data values for the second unit using decoded data for the first unit of memory produced by the second decoding operation.

3. The method of claim 1, wherein the set of remedial operations includes:

updating a respective soft information value for the second unit of memory, corresponding to uncorrectable errors in the second unit of memory, in accordance with;

a magnitude of a corresponding soft information value for the first unit of memory; and

a direction based on parity of the error correction stripe excluding the second unit of memory; and

performing a third decoding operation on data obtained from at least a portion of the second unit using the updated soft information value for the second unit of memory; and

in accordance with a determination that the third decoding operation is successful, generating corrected data values for the first unit of memory using decoded data for the second unit of memory produced by the third decoding operation.

4. The method of claim 1, wherein the set of remedial operations includes:

further updating a respective soft information value for the first unit of memory, corresponding to uncorrectable errors in the first unit of memory, in accordance with;

a magnitude of a corresponding soft information value for a third unit of the two or more units of memory that include uncorrectable errors; and

a direction based on parity of the error correction stripe excluding the first unit of memory; and

performing a further decoding operation on data obtained from at least a portion of the first unit of memory using the updated soft information value.

5. The method of claim 1, wherein the error correction stripe includes a parity unit that stores one or more parity values based on at least data in the first unit and the second unit.

6. The method of claim 5, wherein the error correction stripe is a RAID stripe.

7. The method of claim 1, wherein the soft information values comprise log-likelihood ratios (LLRs).

8. The method of claim 1, wherein the units of memory comprise one of partial pages, pages, codewords, partial codewords, blocks, and die planes.

9. The method of claim 1, wherein the units of memory comprise non-volatile memory.

10. The method of claim 1, wherein the units of memory comprise flash memory.

11. The method of claim 1, wherein the first decoding operations and the second decoding operation comprise low-density parity check (LDPC) decoding operations.

12. The method of claim 1, wherein updating the respective soft information value for the first unit of memory comprises calculating, as the updated soft information value, a linear combination of:

the respective soft information value; and

an update term calculated in accordance with the magnitude of the corresponding soft information value for the second unit of memory and the direction based on parity of the error correction stripe excluding the first unit of memory.

13. A storage device, comprising:

non-volatile memory;

one or more processors;

a decoder for decoding data obtained from the non-volatile memory, including first decoding operations on data obtained from a plurality of units of the non-volatile memory using soft information values for the plurality of units of the non-volatile memory, wherein the plurality of units of the non-volatile memory includes an error correction stripe; and

controller memory storing one or more programs, which when executed by the one or more processors cause the storage device to perform operations comprising;

determining that two or more of the plurality of units of the non-volatile memory have uncorrectable errors, wherein the uncorrectable errors are uncorrectable using the first decoding operations;

updating a respective soft information value for a first unit of memory in accordance with;

a magnitude of a corresponding soft information value for a second unit of memory; and

a direction based on parity of the error correction stripe excluding the first unit of memory, wherein the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors; and

wherein the decoder is further for a second decoding operation on data obtained from at least a portion of the first unit of memory using the updated soft information value; and

in accordance with a determination that the second decoding operation is successful, the decoder is further for providing decoded data from the second decoding operation to a memory controller; and

in accordance with a determination that the second decoding operation is unsuccessful, the decoder is further for performing a set of remedial operations or providing an indication of an irresolvable error condition to a memory controller.

14. The storage device of claim 13, wherein the memory controller includes the one or more processors and controller memory, and wherein the memory controller includes a soft information adjustment module that adjusts soft information values of respective units of the non-volatile memory.

15. The storage device of claim 13, wherein, in accordance with the determination that decoding data obtained from at least a portion of the first unit of memory using the updated soft information value is successful, the one or more processors cause the storage device to generate corrected data values for the second unit using decoded data for the first unit of memory produced by the second decoding operation.

16. The storage device of claim 13, wherein the set of remedial operations includes:

updating a respective soft information value for the second unit of memory, corresponding to uncorrectable errors in the second unit of memory, in accordance with;

a magnitude of a corresponding soft information value for the first unit of memory; and

a direction based on parity of the error correction stripe excluding the second unit of memory; and

performing a third decoding operation on data obtained from at least a portion of the second unit using the updated soft information value for the second unit of memory; and

in accordance with a determination that the third decoding operation is successful, generating corrected data values for the first unit of memory using decoded data for the second unit of memory produced by the third decoding operation.

17. The storage device of claim 13, wherein the error correction stripe includes a parity unit that stores one or more parity values based on at least data in the first unit and the second unit.

18. The storage device of claim 17, wherein the error correction stripe is a RAID stripe.

19. The storage device of claim 13, wherein the soft information values comprise log-likelihood ratios (LLRs).

20. The storage device of claim 13, wherein updating the respective soft information value for the first unit of memory comprises calculating, as the updated soft information value, a linear combination of:

the respective soft information value; and

an update term calculated in accordance with the magnitude of the corresponding soft information value for the second unit of memory and the direction based on parity of the error correction stripe excluding the first unit of memory.

21. A non-transitory computer readable storage medium, storing one or more programs configured for execution by one or more processors of a storage system, the one or more programs including instructions for:

at a storage device;

performing first decoding operations on a plurality of units of memory using soft information values for the plurality of units of memory, wherein the plurality of units of memory includes an error correction stripe;

determining that two or more of the plurality of units of memory have uncorrectable errors, wherein the uncorrectable errors are uncorrectable using the first decoding operations;

updating a respective soft information value for a first unit of memory in accordance with;

a magnitude of a corresponding soft information value for a second unit of memory; and

a direction based on parity of the error correction stripe excluding the first unit of memory, wherein the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors;

performing a second decoding operation on data obtained from at least a portion of the first unit of memory using the updated soft information value;

in accordance with a determination that the second decoding operation is successful, providing decoded data from the second decoding operation to a memory controller; and

in accordance with a determination that the second decoding operation is unsuccessful, performing a set of remedial operations or providing an indication of an irresolvable error condition to a memory controller.