Memory-mapped state bus for integrated circuit

• US 10,372,655 B1
• Filed: 03/20/2017
• Issued: 08/06/2019
• Est. Priority Date: 10/29/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Perry, Steven
• Primary Examiner(s): Thammavong, Prasith
• Application Number:
  US15/463,993
• Time in Patent Office: 869 Days
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures

Abstract

Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

Claims

1. A system comprising:

an integrated circuit comprising data utilization circuitry, wherein the data utilization circuitry comprises;

a plurality of logic blocks; and

a broadcast bus coupled to the plurality of logic blocks, wherein the broadcast bus is configured to broadcast an addressed message to each logic block of the plurality of logic blocks; and

a configurator device comprising one or more processors configured to;

receive a logic design for the plurality of logic blocks;

based at least in part on the logic design, assign logic block addresses to the plurality of logic blocks such that logic blocks of the plurality of logic blocks are balanced along the broadcast bus, wherein each logic block of the plurality of logic blocks disposed on a first side of the broadcast bus corresponds to a respective logic block of the plurality of logic blocks disposed on a second side of the broadcast bus; and

program the logic design into the integrated circuit.

2. The system of claim 1, wherein the addressed message comprises content and a target address.

3. The system of claim 2, wherein each logic block of the plurality of logic blocks receives the addressed message from the broadcast bus and uses the content of the addressed message only when the target address matches an address assigned to that logic block.

4. The system of claim 3, wherein each logic block of the plurality of logic blocks comprises a read back block that enables or disables that logic block from sending a reply message when the logic block uses the content of the addressed message and the content instructs the logic block to send the reply message.

5. The system of claim 4, wherein two or more logic blocks of the plurality of logic blocks are assigned the same address.

6. The system of claim 5, wherein the read back blocks of the two or more logic blocks assigned the same address permit only one of the two or more logic blocks to send the reply message.

7. The system device of claim 1, wherein the data utilization circuitry comprises a field programmable gate array (FPGA) fabric.

8. The system device of claim 1, wherein the data utilization circuitry comprises application-specific logic of the integrated circuit.

9. The system device of claim 1, wherein the plurality of logic blocks comprises a digital signal processor (DSP) block, a memory block, a logical array block (LAB), or any combination thereof.

10. An integrated circuit comprising:

a broadcast bus configured to broadcast an addressed message comprising content and a target address, wherein the broadcast bus comprises

a plurality of addressed logic blocks coupled to the broadcast bus wherein the plurality of addressed logic blocks are balanced along the broadcast bus, wherein each addressed logic block of the plurality of addressed logic blocks disposed on a first side of the broadcast bus corresponds to a respective addressed logic block of the plurality of addressed logic blocks disposed on a second side of the broadcast bus.

11. The integrated circuit of claim 10, wherein a first addressed logic block of the plurality of addressed logic blocks and a second addressed logic block of the plurality of addressed logic blocks are positioned symmetrically about a centerline of the broadcast bus.

12. The integrated circuit of claim 11, wherein the first addressed logic block is positioned on a first branch of the broadcast bus and the second addressed logic block is positioned on a second branch of the broadcast bus.

13. A method comprising:

receiving, via one or more processors, a logic design for programmable fabric of a programmable logic device, wherein logic blocks of the programmable fabric are accessible by a hardware broadcast bus;

based at least in part on the logic design, assigning, via the one or more processors, logic block addresses to logic blocks such that logic blocks are balanced along the hardware broadcast bus, wherein each logic block of the plurality of logic blocks disposed on a first side of the broadcast bus corresponds to a respective logic block of the plurality of logic blocks disposed on a second side of the broadcast bus; and

programming, via the one or more processors, the logic design into the programmable logic device.

14. The method of claim 13, comprising setting, via the one or more processors, a read back flag on only one logic block of each group of logic blocks that share the same logic block address to enable the only one logic block of each group to read back data when so requested.

15. The method of claim 13, wherein assigning, via the one or more processors, logic block addresses, occurs explicitly.

16. The method of claim 13, wherein assigning, via the one or more processors, the logic block addresses, occurs implicitly.

17. The method of claim 13, comprising representing, via the one or more processors, the logic block addresses by register transfer level parameters.

18. The method of claim 13, comprising inserting, via the one or more processors, the logic block addresses into a start-of-frame stream.

19. The method of claim 13, wherein assigning, via the one or more processors, the logic block addresses is based at least in part on simulating operation of the programmable logic device using cross-hierarchy signals.