Device including structure over airgap

• US 10,381,801 B1
• Filed: 04/26/2018
• Issued: 08/13/2019
• Est. Priority Date: 04/26/2018
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Liang, Di
• Primary Examiner(s): Park, Kinam
• Application Number:
  US15/963,543
• Time in Patent Office: 474 Days
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01S 2301/173 The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 5/0206 Substrates, e.g. growth, shape, material, removal or bonding; specific crystal orientation H01S5/3202
• CPC Class Codes: H01S 5/0607 by varying physical parameters other than the potential of the electrodes, e.g. by an electric or magnetic field, mechanical deformation, pressure, light, temperature
• CPC Class Codes: H01S 5/0614 controlled by electric field, i.e. whereby an additional electric field is used to tune the bandgap, e.g. using the Stark-effect
• CPC Class Codes: H01S 5/11 Comprising a photonic bandgap structure
• CPC Class Codes: H01S 5/18316 Airgap confined
• CPC Class Codes: H01S 5/18363 comprising air layers
• CPC Class Codes: H01S 5/18369 based on dielectric materials
• CPC Class Codes: H01S 5/18377 comprising layers of different kind of materials, e.g. combinations of semiconducting with dielectric or metallic layers
• CPC Class Codes: H01S 5/2045 employing free standing waveguides or air gap confinement
• CPC Class Codes: H01S 5/22 having a ridge or stripe structure
• CPC Class Codes: H01S 5/2206 based on III-V materials
• CPC Class Codes: H01S 5/223 Buried stripe structure H01S5/227 takes precedence
• CPC Class Codes: H01S 5/3013 AIIIBV compounds
• CPC Class Codes: H01S 5/32 comprising PN junctions, e.g. hetero- or double- heterostructures H01S5/34, H01S5/36 take precedence
• CPC Class Codes: H01S 5/323 in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

Abstract

A device comprises a substrate, a sacrificial material layer over the substrate, a first solid-state material layer over the sacrificial layer, a dielectric layer over solid-state material layer, and a second solid-state material layer over the dielectric layer. The sacrificial material layer may have an airgap, the solid-state material layer may comprise a structure over the airgap and may be separated from a bulk portion of the first material layer by trenches, where the trenches extend to the airgap.

Claims

1. A device, comprising:

a substrate;

a sacrificial material layer over the substrate, the sacrificial material layer having an airgap;

a first solid-state material layer over the sacrificial layer, the solid-state material layer comprising a structure over the airgap and separated from a bulk portion of the first material layer by trenches, the trenches extending to the airgap;

a dielectric layer over solid-state material layer;

a second solid-state material layer over the dielectric layer.

2. The device of claim 1, wherein the airgap extends below a portion of the bulk portion of the first solid-state material layer.

3. The device of claim 1, wherein the structure is a passive photonic device.

4. The device of claim 3, wherein the structure is a waveguide.

5. The device of claim 4, wherein the structure is a rib waveguide.

6. The device of claim 1, wherein the structure, the dielectric, and second solid-state material layer form a capacitor.

7. The device of claim 1, further comprising a mesa over the second solid-state material layer.

8. The device of claim 7, wherein the second solid-state material layer has a first crystal structure and mesa comprises a solid-state material having a second crystal structure with a matching lattice with the first crystal structure.

9. The device of claim 8, wherein the mesa comprises the same solid-state material as the second solid-state material layer and the first crystal structure is the same as the second crystal structure.

10. The device of claim 1, further comprising an active photonic device over the second solid-state material layer and the airgap.

11. The device of claim 10, wherein the active photonic device is within a vertical boundary defined by the trenches.

12. The device of claim 1, further comprising a second dielectric layer over the first dielectric layer.

13. The device of claim 1, wherein the first material layer comprises an oxide, the first solid-state material layer comprises silicon, and the second solid-state material layer comprises a III-V material.

14. The device of claim 1, wherein the airgap extends through the entire sacrificial material layer.

15. A method, comprising:

forming trenches extending to a sacrificial material layer in a first solid-state material layer such that the trenches define a structure separated from a bulk portion of the first material layer;

using the trenches to selectively remove a portion of the sacrificial material layer to form an airgap underneath the structure;

disposing a dielectric layer over the first solid-state material layer; and

bonding a wafer comprising a second solid-state material layer to an assembly comprising the sacrificial material layer and the first solid-state material layer.

16. The method of claim 15, further comprising:

forming a mesa on the second solid-state material layer over the airgap.

17. The method of claim 16, wherein the mesa comprises the same material as the second solid-state material layer.

18. The method of claim 16, further comprising coupling a voltage source to a capacitor formed from a portion of the mesa and the structure.

19. The method of claim 15, wherein disposing the dielectric layer over the first solid-state material layer comprises depositing a first dielectric layer over the first solid-state material layer.

20. The method of claim 19, further comprising depositing a second dielectric layer on the wafer, and wherein bonding the wafer comprises bonding the second dielectric layer to the first dielectric layer.