Placement of vias in printed circuit board circuits

• US 10,383,213 B1
• Filed: 02/22/2019
• Issued: 08/13/2019
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Chengson, David P., Chang, Edward C., Doppalapudi, Ranjeeth, Pappu, Santosh Kumar
• Primary Examiner(s): Nguyen, Hoa C
• Application Number:
  US16/283,119
• Time in Patent Office: 172 Days
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/0251 related to vias or transitions between vias and transmission lines
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10015 Non-printed capacitor
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4038 Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence

Abstract

In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

Claims

1. An electronic device comprising a printed circuit board (PCB) device, the PCB device comprising:

a first trace on a first layer;

a second trace on a second layer, wherein the second trace is electrically isolated from the first trace;

a first trace via including a first pad on the first layer, wherein the first pad is electrically connected to the first trace;

a second trace via including a second pad on the second layer, wherein the second pad is electrically connected to the second trace;

an antipad surrounding the first trace via and the second trace via;

a first ground via through the first layer and electrically connected to a ground plane, wherein the first ground via includes a first ground pad on the first layer positioned between the first trace and the second trace;

a second ground via through the first layer and electrically connected to the ground plane, wherein the second ground via includes a second ground pad on the first layer, wherein the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad;

a third ground via through the first layer and electrically connected to the ground plane, wherein the third ground via includes a third ground pad on the first layer;

a fourth ground via through the first layer and electrically connected to the ground plane, wherein the fourth ground via includes a fourth ground pad on the first layer, wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

2. The electronic device of claim 1, wherein the antipad comprises a first antipad, wherein the perpendicular bisector is a first perpendicular bisector, and wherein the PCB device further comprises:

a third trace on the first layer, wherein the third trace is electrically isolated from the first trace and the second trace;

a fourth trace on the second layer, wherein the fourth trace is electrically isolated from the first trace, the second trace, and the third trace;

a third trace via including a third pad on the first layer, wherein the third pad is electrically connected to the third trace;

a fourth trace via including a fourth pad on the second layer, wherein the fourth pad is electrically connected to the fourth trace;

a second antipad surrounding the third trace via and the fourth trace via;

a fifth ground via electrically connected to the ground plane, wherein the fifth ground via includes a fifth ground pad on the first layer positioned between the third trace and the fourth trace;

a sixth ground via electrically connected to the ground plane, wherein the sixth ground via includes a sixth ground pad on the first layer, wherein the fifth ground pad and the sixth ground pad are approximately symmetrically positioned about a second perpendicular bisector of a line from the third pad to the fourth pad;

a seventh ground via electrically connected to the ground plane, wherein the seventh ground via includes a seventh ground pad on the first layer; and

an eighth ground via electrically connected to the ground plane, wherein the eighth ground via includes an eighth ground pad on the first layer, wherein the seventh ground pad and the eighth ground pad are approximately symmetrically positioned about the second perpendicular bisector.

3. The electronic device of claim 2, wherein a center-on-center spacing from the first antipad to the second antipad is less than three millimeters.

4. The electronic device of claim 2, wherein:

the third trace via is configured to generate first electromagnetic noise,

the fourth trace via is configured to generate second electromagnetic noise, and

wherein an effect of the first electromagnetic noise on the first trace via is approximately equal to an effect of the second electromagnetic noise on the second trace via.

5. The electronic device of claim 2, wherein the PCB device further comprises:

a fifth trace on the first layer, wherein the fifth trace is electrically isolated from the first trace and the second trace;

a sixth trace on the second layer, wherein the sixth trace is electrically isolated from the first trace, the second trace, and the fifth trace;

a fifth trace via including a fifth pad on the first layer, wherein the fifth pad is electrically connected to the fifth trace;

a sixth trace via including a sixth pad on the second layer, wherein the sixth pad is electrically connected to the sixth trace;

a third antipad surrounding the fifth trace via and the sixth trace via;

a ninth ground via electrically connected to the ground plane, wherein the ninth ground via includes a ninth ground pad on the first layer positioned between the fifth trace and the sixth trace;

a tenth ground via electrically connected to the ground plane, wherein the tenth ground via includes a tenth ground pad on the first layer, wherein the ninth ground pad and the tenth ground pad are approximately symmetrically positioned about a third perpendicular bisector of a line from the fifth pad to the sixth pad;

an eleventh ground via electrically connected to the ground plane, wherein the eleventh ground via includes an eleventh ground pad on the first layer; and

a twelfth ground via electrically connected to the ground plane, wherein the twelfth ground via includes a twelfth ground pad on the first layer, wherein the eleventh ground pad and the twelfth ground pad are approximately symmetrically positioned about the third perpendicular bisector.

6. The electronic device of claim 5, wherein a center-on-center spacing from the second antipad to the third antipad is less than three millimeters.

7. The electronic device of claim 1, wherein:

a longest dimension of the antipad measured across the antipad is greater than fifteen hundred micrometers and less than three millimeters; and

a shortest dimension of the antipad measured across the antipad is greater than seven hundred and fifty micrometers and less than fifteen hundred micrometers.

8. The electronic device of claim 1, wherein the PCB device further comprises:

a first capacitor electrically connected in series with the first trace; and

a second capacitor electrically connected in series with the second trace.

9. The electronic device of claim 1, wherein:

a center-on-center spacing from a center of the first pad to a center of the first ground pad is less than fifteen hundred micrometers;

a center-on-center spacing from the second pad to the second ground pad is less than fifteen hundred micrometers.

10. The electronic device of claim 1, wherein the first layer and the second layer are a same layer.

11. The electronic device of claim 1, wherein the first layer and the second layer are different layers.

12. A method for constructing a printed circuit board (PCB), the method comprising:

drilling a first trace via, a second trace via, a first ground via, a second ground via, a third ground via, and a fourth ground via in the PCB;

filling the first trace via, a second trace via, a first ground via, a second ground via, a third ground via, and a fourth ground via with conductive material;

forming a first pad on a first layer of the PCB that is electrically connected to the conductive material of the first trace via;

forming a second pad on a second layer that is electrically connected to the conductive material of the second trace via;

forming a first ground pad on the first layer that is electrically connected to the conductive material of the first ground via, wherein the first ground pad is positioned between the first trace and the second trace;

forming a second ground pad on the first layer that is electrically connected to the conductive material of the second ground via, wherein the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad;

forming a third ground pad on the first layer that is electrically connected to the conductive material of the third ground via;

forming a fourth ground pad on the first layer that is electrically connected to the conductive material of the fourth ground via, wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector;

etching an antipad surrounding the first trace via and the second trace via; and

forming a first trace on the first layer and a second trace on the second layer, wherein the first trace is electrically connected to the first pad, and wherein the second trace is electrically connected to the second pad.

13. The method of claim 12, wherein:

a longest dimension of the antipad is greater than fifteen hundred micrometers and less than three millimeters; and

a shortest dimension of the antipad that is greater than eight hundred micrometers and less than fifteen hundred micrometers.

14. The method of claim 12, wherein the first layer and the second layer are a same layer.

15. The method of claim 12, wherein the first layer and the second layer are different layers.