Semiconductor device having an active trench and a body trench

• US 10,388,776 B2
• Filed: 11/13/2018
• Issued: 08/20/2019
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Cotorogea, Maria, Wolter, Frank, Schulze, Hans-Joachim, Niedernostheide, Franz-Josef, Gawlina-Schmidl, Yvonne
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US16/189,279
• Publication Number:
  US 20190103480A1
• Time in Patent Office: 280 Days
• Field of Search: 257139, 257320, 257330-334, 257329, 257E27091, 438270, 438271, 438587, 438588
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first main surface;

a drift region of a first conductivity type formed in the semiconductor substrate;

a body region of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate above the drift region;

an active gate trench extending from the first main surface and into the body region, the active gate trench including a first electrode coupled to a gate potential;

a source region of the first conductivity type formed in the body region adjacent to the gate trench and coupled to a source potential;

a first body trench extending from the first main surface and into the body region, the first body trench including a second electrode coupled to the source potential; and

an inactive gate trench extending from the first main surface and into the body region, the inactive gate trench including a third electrode coupled to the gate potential,

wherein a conductive channel is present along the active gate trench in case of the gate potential being at an on-voltage of the semiconductor device,

wherein no conductive channel is present along the inactive gate trench in case of the gate potential being at the on-voltage.

2. The semiconductor device of claim 1, wherein a distance between the first body trench and the active gate trench is smaller than a distance between the inactive gate trench and the active gate trench.

3. The semiconductor device of claim 1, further comprising a gate insulating layer at sidewalls and at a bottom side of the active gate trench, wherein a thickness of the gate insulating layer is smaller than a thickness of an insulating layer in the first body trench and/or the inactive gate trench.

4. The semiconductor device of claim 1, further comprising an insulating layer at sidewalls and at a bottom side of the first body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench.

5. The semiconductor device of claim 4, wherein a thickness of the insulating layer in the first body trench on a sidewall adjacent the active gate trench is different from the thickness of the insulating layer on the sidewall remote from the active gate trench.

6. The semiconductor device of claim 4, wherein a composition of the insulating layer in the first body trench at a sidewall adjacent the active gate trench is different from the composition of the insulating layer at the sidewall remote from the active gate trench.

7. The semiconductor device of claim 1, further comprising additional body trenches, the additional body trenches being different from the active gate trench.

8. The semiconductor device of claim 7, wherein an insulating layer is disposed in each of the additional body trenches, and wherein a thickness of the insulating layer disposed in the additional body trenches is different from a thickness of a gate insulating layer in the active gate trench.

9. The semiconductor device of claim 7, wherein a first thickness of the insulating layer in one of the body trenches at a sidewall adjacent the active gate trench is different from a second thickness of the insulating layer at the sidewall remote from the active gate trench, wherein the first thickness is approximately equal to a thickness of a gate insulating layer in the active gate trench, and wherein the second thickness is approximately equal to the thickness of the insulating layer in the additional body trenches.

10. The semiconductor device of claim 7, wherein the additional body trenches each include an electrode coupled to the source potential.

11. A semiconductor device, comprising:

a semiconductor substrate having a first main surface;

a drift region of a first conductivity type formed in the semiconductor substrate;

a body region of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate above the drift region; and

a transistor cell comprising;

an active gate trench extending from the first main surface and into the body region, the active gate trench including a first electrode coupled to a gate potential;

a source region of the first conductivity type formed in the body region adjacent to the gate trench and coupled to a source potential;

a first body trench extending from the first main surface and into the body region, the first body trench including a second electrode coupled to the source potential; and

an inactive gate trench extending from the first main surface and into the body region, the inactive gate trench including a third electrode coupled to the gate potential,

wherein a conductive channel of the transistor cell is present along the active gate trench in case of the gate potential being at an on-voltage of the semiconductor device,

wherein no conductive channel of the transistor cell is present along the inactive gate trench in case of the gate potential being at the on-voltage.

12. The semiconductor device of claim 11, wherein a distance between the first body trench and the active gate trench of the transistor cell is smaller than a distance between the inactive gate trench and the active gate trench of the transistor cell.

13. The semiconductor device of claim 11, wherein the transistor cell further comprises a gate insulating layer at sidewalls and at a bottom side of the active gate trench, and wherein a thickness of the gate insulating layer is smaller than a thickness of an insulating layer in the first body trench and/or the inactive gate trench of the transistor cell.

14. The semiconductor device of claim 11, wherein the transistor cell further comprises an insulating layer at sidewalls and at a bottom side of the first body trench, and wherein the insulating layer is asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench.

15. The semiconductor device of claim 14, wherein a thickness of the insulating layer in the first body trench on a sidewall adjacent the active gate trench of the transistor cell is different from the thickness of the insulating layer on the sidewall remote from the active gate trench of the transistor cell.

16. The semiconductor device of claim 14, wherein a composition of the insulating layer in the first body trench at a sidewall adjacent the active gate trench of the transistor cell is different from the composition of the insulating layer at the sidewall remote from the active gate trench of the transistor cell.

17. The semiconductor device of claim 11, wherein the transistor cell further comprises additional body trenches, and wherein the additional body trenches are different from the active gate trench of the transistor cell.

18. The semiconductor device of claim 17, wherein the transistor cell comprises an insulating layer disposed in each of the additional body trenches, and wherein a thickness of the insulating layer disposed in the additional body trenches is different from a thickness of a gate insulating layer in the active gate trench of the transistor cell.

19. The semiconductor device of claim 17, wherein a first thickness of the insulating layer in one of the body trenches at a sidewall adjacent the active gate trench of the transistor cell is different from a second thickness of the insulating layer at the sidewall remote from the active gate trench of the transistor cell, wherein the first thickness is approximately equal to a thickness of a gate insulating layer in the active gate trench of the transistor cell, and wherein the second thickness is approximately equal to the thickness of the insulating layer in the additional body trenches of the transistor cell.

20. The semiconductor device of claim 17, wherein the additional body trenches of the transistor cell each include an electrode coupled to the source potential.