Module auto addressing in platform bus
First Claim
1. A module addressing mechanism comprising:
- a platform bus;
a base module on the platform bus; and
one or more modules besides the base module on the platform bus; and
wherein;
the base module is designated as a master on the platform bus;
the one or more modules besides the base model are designated as slaves on the platform bus;
the modules do not assume a device address when put on the platform bus;
the base module puts virtually all of the modules that are slaves into an addressing mode by broadcasting a first message on the platform bus, wherein the first message includes a first proprietary frame message that distinguishes the first message from normal traffic data; and
after each of virtually all of the modules that are slaves on the platform bus has an assigned address, the base module directs all of the modules to leave the address mode by broadcasting a second message on the platform bus, wherein the second message includes a second proprietary frame message that distinguishes the second message from normal traffic data; and
the modules are dynamically assigned addresses by an algorithm at boot time of the base module.
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Accused Products
Abstract
A system and approach for addressing modules on a platform bus that may incorporate a master module and one or more slave modules. The platform bus may run through sub-base connectors that interlock modules together on a rail. Addressing of the modules may occur automatically and dynamically in that the master module may have a first address by default, and a first slave module adjoining the master module may be assigned a second address. A second slave module adjoining the first slave module, if there is one, may be assigned a third address. Each of the other slave modules, adjoining a preceding slave module assigned an address, may be assigned a next address after an address assigned to a preceding slave module. Addresses may be assigned in a numerical order to each module based on a physical position of the respective module on a rail.
149 Citations
19 Claims
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1. A module addressing mechanism comprising:
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a platform bus; a base module on the platform bus; and one or more modules besides the base module on the platform bus; and wherein; the base module is designated as a master on the platform bus; the one or more modules besides the base model are designated as slaves on the platform bus; the modules do not assume a device address when put on the platform bus; the base module puts virtually all of the modules that are slaves into an addressing mode by broadcasting a first message on the platform bus, wherein the first message includes a first proprietary frame message that distinguishes the first message from normal traffic data; and after each of virtually all of the modules that are slaves on the platform bus has an assigned address, the base module directs all of the modules to leave the address mode by broadcasting a second message on the platform bus, wherein the second message includes a second proprietary frame message that distinguishes the second message from normal traffic data; and the modules are dynamically assigned addresses by an algorithm at boot time of the base module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for addressing modules on a platform bus comprising:
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obtaining a master module on a platform bus; adding one or more slave modules on the platform bus; and running an identification signal line through the modules via the sub-base connectors; and wherein; the platform bus is a wire network that runs through sub-base connectors that interlock the modules together; addressing of the modules occurs automatically in that the master module has a first address by default, and a first slave module adjoining the master module is assigned a second address, wherein the addressing of the modules is automatically performed by an algorithm at boot time of the base module; a second slave module nearest to the first slave module, if there is a second slave module, is assigned a third address; each of the other slave modules, nearest to a preceding slave module assigned an address, is assigned a next address after an address assigned to the preceding slave module; the master module puts virtually all of the slave modules into an addressing mode by broadcasting a first message on the platform bus, wherein the first message includes a first proprietary frame message that distinguishes the first message from normal traffic data; and after each of virtually all of the slave modules on the platform bus has an assigned address, the master module directs all of the slave modules to leave the address mode by broadcasting a second message on the platform bus, wherein the second message includes a second proprietary frame message that distinguishes the second message from normal traffic data. - View Dependent Claims (11, 12, 13, 14)
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15. A module system having addressing comprising:
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a bus; a master module on the bus; and one or more slave modules on the bus; and wherein; the master module comprises a processor; an algorithm for assigning unique addresses to the modules is automatically performed at the processor at boot-time of the master module; wherein the algorithm instructs the master module to put the one or more slave modules into an addressing mode by broadcasting a first message on the bus, wherein the first message includes a first proprietary frame message that distinguishes the first message from normal traffic data; and after each of virtually of the one or more slave modules has an assigned address, the master module directs the one or more slave modules to leave the address mode by broadcasting a second message on the bus, wherein the second message includes a second proprietary frame message that distinguishes the second message from normal traffic data. - View Dependent Claims (16, 17, 18, 19)
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Specification