Systems and methods utilizing serial configurations of magnetic memory devices

• US 10,403,343 B2
• Filed: 12/29/2017
• Issued: 09/03/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Bozdag, Kadriye Deniz, Gajek, Marcin, El Baraji, Mourad, Ryan, Eric Michael
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/859,250
• Publication Number:
  US 20190206465A1
• Time in Patent Office: 613 Days
• Field of Search: 365158, 365171, 365173, 365 63
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Claims

1. An apparatus comprising:

two or more perpendicular magnetic tunnel junctions (pMTJs), including a first pMTJ having a first magnetic characteristic and a first electrical characteristic and a second pMTJ having a second magnetic characteristic and a second electrical characteristic, wherein;

the first magnetic characteristic is distinct from the second magnetic characteristic;

the first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first pMTJ; and

the second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second pMTJ;

a transistor having three terminals, wherein the first pMTJ is coupled to a first terminal of the three terminals; and

a metallic separator coupling the first pMTJ with the second pMTJ, wherein the first pMTJ and the second pMTJ are arranged in series.

2. The apparatus of claim 1, wherein each respective pMTJ has a respective magnetic characteristic determined by one or more material compositions of the respective pMTJ, wherein the material compositions include materials selected from the group consisting of MgO, CoFeB, Cobalt, Platinum, Ruthenium, Tungsten, and Tantalum.

8. The apparatus of claim 1, wherein each respective pMTJ has a distinct switching current value which is determined by the magnetic characteristic of the respective pMTJ.

9. The apparatus of claim 1, further comprising:

a third pMTJ having a third magnetic characteristic and a third electrical characteristic, wherein the third magnetic characteristic is distinct from the first magnetic characteristic and the second magnetic characteristic; and

a second metallic separator coupling the third pMTJ with the second pMTJ, wherein the first pMTJ, the second pMTJ, and the third pMTJ are arranged in series.

10. The apparatus of claim 1, wherein a total resistance measured across the two or more pMTJs may have a maximum of 2{circumflex over ( 

)}n discrete values, where n is a number of pMTJs of the two or more pMTJs.

11. The apparatus of claim 10, wherein the two or more pMTJs can store a fewer number of bits than the maximum of 2{circumflex over ( 

)}n discrete values.

13. The apparatus of claim 1, wherein the apparatus is responsive to a single or multi-level voltage pulse for writing one or more bits to the two or more pMTJs, wherein writing the one or more bits changes a magnetic state of the first pMTJ.

14. The apparatus of claim 13, wherein the magnetic state of the first pMTJ is a parallel magnetic state or an anti-parallel magnetic state.

3. An apparatus comprising:

two or more perpendicular magnetic tunnel junctions (pMTJs), including a first pMTJ having a first magnetic characteristic and a first electrical characteristic and a second pMTJ having a second magnetic characteristic and a second electrical characteristic, wherein;

the first magnetic characteristic is distinct from the second magnetic characteristic;

the first electrical characteristic of the first pMTJ is a first resistance determined based on a geometric property of the first pMTJ and a Resistance×

Area product (RA product) of the first pMTJ;

the second electrical characteristic of the second pMTJ is a second resistance determined based on a geometric property of the second pMTJ and an RA product of the second pMTJ;

a transistor having three terminals, wherein the first pMTJ is coupled to a first terminal of the three terminals; and

a metallic separator coupling the first pMTJ with the second pMTJ, wherein the first pMTJ and the second pMTJ are arranged in series.

4. The apparatus of claim 3, wherein the first electrical characteristic is distinct from the second electrical characteristic.

5. The apparatus of claim 3, wherein the first electrical characteristic has the same value as the second electrical characteristic.

6. The apparatus of claim 3, wherein the geometric property of each pMTJ is selected from the group consisting of area, diameter, width and thickness.

7. The apparatus of claim 3, wherein the geometric property of each pMTJ is based on an order of stacking a reference layer, a spacer layer, and a storage layer of each pMTJ.

12. An apparatus comprising:

two or more perpendicular magnetic tunnel junctions (pMTJs), including a first pMTJ having a first magnetic characteristic and a first electrical characteristic and a second pMTJ having a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic;

a transistor having three terminals, wherein the first pMTJ is coupled to a first terminal of the three terminals; and

a metallic separator coupling the first pMTJ with the second pMTJ, wherein;

the first pMTJ and the second pMTJ are arranged in series;

the first pMTJ is arranged in an offset position from the second pMTJ so as to minimize influence of stray fields between the first and second pMTJs.

15. The apparatus of claim 12, wherein the apparatus is responsive to instructions for reading a resistance across the two or more pMTJs to determine one or more bits that are stored in each pMTJ of the two or more pMTJs.

16. The apparatus of claim 12, wherein the first pMTJ is in a first magnetic state and the second pMTJ is in the first magnetic state, which creates a first resistance measured across the first pMTJ and the second pMTJ.

17. The apparatus of claim 16, wherein the first pMTJ is in a second magnetic state and the second pMTJ is in the first magnetic state, creating a second resistance, measured across the first pMTJ and the second pMTJ, distinct from the first resistance.

18. The apparatus of claim 17, wherein the first pMTJ is in the first magnetic state and the second pMTJ is in the second magnetic state, creating a third resistance, measured across the first pMTJ and the second pMTJ, distinct from the first resistance and the second resistance.

19. The apparatus of claim 18, wherein the first pMTJ is in the second magnetic state and the second pMTJ is in the second magnetic state, creating a fourth resistance, measured across the first pMTJ and the second pMTJ, distinct from the first resistance, the second resistance, and the third resistance.

20. The apparatus of claim 12, wherein a total resistance measured across the first pMTJ and the second pMTJ is discrete based on a magnetic state of the first pMTJ and the magnetic state of the second pMTJ.

21. The apparatus of claim 12, wherein two or more pMTJs may have a maximum of 2{circumflex over ( 

)}n bits stored, where n is a number of pMTJs of the two or more pMTJs.