Asymmetric multi-core processor with native switching mechanism

• US 10,423,216 B2
• Filed: 11/12/2013
• Issued: 09/24/2019
• Est. Priority Date: 03/26/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Hooker, Rodney E., Parks, Terry, Henry, G. Glenn
• Primary Examiner(s): Puente, Emerson C
• Assistant Examiner(s): Mills, Paul V
• Application Number:
  US14/077,740
• Publication Number:
  US 20140298060A1
• Time in Patent Office: 2,142 Days
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

Claims

1. A processor having an instruction set architecture (ISA) which supports a set of features including a wide bit-width operating mode and a narrow bit-width operating mode, wherein the wide bit-width operating mode is wider than the narrow bit-width operating mode and wherein the ISA specifies a particular value to be written to an identified control register in order to set the current bit-width operating mode of a processing core, the processor comprising:

a first processing core configured to support the wide bit-width operating mode and the narrow bit-width operating mode;

a second processing core configured to support at least the narrow bit-width operating mode and configured to execute a thread by consuming less power but with lower performance than the first processing core; and

a switch manager integrated into the first processing core configured to;

detect a thread fetched by the first core has switched from the wide bit-width operating mode to the narrow bit-width operating mode by detecting the particular value being written into the identified control register by the thread;

cause, in response to the detecting, microcode in the first processing core to save an execution state of the thread from the first core to a state storage and instruct the second core to retrieve the saved execution state so that execution can continue by the second processing core; and

instruct the first processing core to enter a low power mode subsequent to instructing the second core.

2. The processor of claim 1, wherein the second processing core is further configured to exit a low power mode prior to retrieving the execution state of the thread.

3. A method performed by a processor having an instruction set architecture (ISA) which supports a set of features including a wide bit-width operating mode and a narrow bit-width operating mode and having first and second processing cores, wherein the wide bit-width operating mode is wider than the narrow bit-width operating mode and the ISA specifies a particular value to be written to an identified control register in order to set the current bit-width operating mode of a processing core, and wherein the first core is configured to support the wide and the narrow bit-width operating modes and the second core is configured to support at least the narrow bit-width operating mode and to execute a thread by consuming less power but with lower performance than the first core, the method comprising:

detecting, by switch manager logic integrated in the first processing core, that a thread executing on the first core has changed from the wide bit-width operating mode to the narrow bit-width operating mode by detecting the particular value being written into the identified control register by the thread, and in response to said detecting;

executing microcode in the first processing core to save current execution state of the thread to a shared state storage memory,

executing microcode in the second processing core to retrieve the saved execution state, in order to transfer the execution of the thread from the first core to the second core, and

instructing the first processing core to enter a low power mode.

4. The method of claim 3, further comprising:

detecting, by switch manager logic integrated in the second processing core, that utilization of the second processing core has gone above a threshold while executing the thread; and

responsively causing the second processing core to save current execution state of the thread to the shared state storage memory, and causing the first processing core to retrieve the saved execution state of the thread in order to transfer the thread state to the first core to continue to execute the thread.

5. A processor having an instruction set architecture (ISA) which supports a set of features including a wide bit-width operating mode and a narrow bit-width operating mode, wherein the wide bit-width operating mode is wider than the narrow bit-width operating mode and the ISA specifies a particular value to be written to an identified control register in order to set the current bit-width operating mode of a processing core, the processor comprising:

a first processing core configured to support the wide bit-width operating mode and the narrow bit-width operating mode;

a second processing core configured to support at least the narrow bit-width operating mode and configured to execute a thread by consuming less power but with lower performance than the first processing core; and

a switch manager integrated into the first and second processing cores configured to;

detect a thread fetched by the first core has switched from the wide bit-width operating mode to the narrow bit-width operating mode by detecting the particular value being written into the identified control register by the thread;

cause, in response to the detecting, microcode in the first processing core to directly transfer an execution state of the thread from the first core to the second core so that execution of the thread can continue by the second processing core; and

instruct the first processing core to enter a low power mode subsequent to the transfer of the execution state.

6. The processor of claim 5, wherein the switch manager is further configured to detect that utilization of the second processing core has gone above a threshold while executing the thread and responsively cause microcode in the second core to directly transfer the thread'"'"'s execution state from the second core to the first core in order to continue to execute the thread on the first core.

7. The processor of claim 5, wherein the second processing core is further configured to exit a low power mode prior to resuming execution of the thread.

8. A method performed by a processor having an instruction set architecture (ISA) which supports a set of features including a wide bit-width operating mode and a narrow bit-width operating mode and having first and second processing cores, wherein the wide bit-width operating mode is wider than the narrow bit-width operating mode and the ISA specifies a particular value to be written to an identified control register in order to set the current bit-width operating mode of a processing core, and wherein the first core is configured to support the wide and the narrow bit-width operating modes and the second core is configured to support at least the narrow bit-width operating mode and to execute a thread by consuming less power but with lower performance than the first core, the method comprising:

detecting, by switch manager logic integrated in the first processing core, that a thread executing on the first core has changed from the wide bit-width operating mode to the narrow bit-width operating mode by detecting the particular value being written into the identified control register by the thread, and in response to said detecting;

executing microcode in the first processing core to directly transfer the thread'"'"'s execution state from the first core to the second core in order to transfer the execution of the thread from the first core to the second core, and

instructing the first processing core to enter a low power mode.

9. The method of claim 8, further comprising:

detecting, by switch manager logic integrated in the second processing core, that utilization of the second processing core has gone above a threshold while executing the thread; and

responsively executing microcode in the second core to directly transfer the thread'"'"'s execution state from the second core to the first processing core in order to continue to execute the thread on the first core.