System and method for scalable processing of abort commands in a host bus adapter system

• US 10,423,333 B2
• Filed: 06/09/2016
• Issued: 09/24/2019
• Est. Priority Date: 01/08/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Zia, Sajid, Krishnamurthy, Viswa, Yeung, Louise
• Primary Examiner(s): Huson, Zachary K
• Application Number:
  US15/178,161
• Publication Number:
  US 20170199667A1
• Time in Patent Office: 1,202 Days
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

An HBA or proxy HBA device is configured to use separate Abort Buffer and I/O Buffer in each channel thereby allowing parallel queuing of regular I/O commands and Abort commands. Processing of Abort commands is prioritized such that Abort commands can be processed before all I/O commands received before the abort command are processed. The use of parallel queuing of regular I/O commands and Abort commands is of particular advantage in systems where multiple channels may receive abort commands simultaneously in the situation where the multiple channels share a common communication resource. In a particular embodiment the abort processing logic is implemented in a fiber channel adapter card which includes a proxy host bus adapter device which connects multiple HBAs via fiber channel to a storage area network.

Claims

1. A host bus adapter system comprising at least 128 of channels, each channel comprising:

a first processing path for processing abort commands;

a first buffer for queuing abort commands in the first processing path;

a second processing path for processing regular I/O commands;

a second buffer for queuing regular I/O commands in the second processing path;

a selector for selecting commands to be processed;

whereby abort commands and regular I/O commands are processed in parallel and the selector is configured to prioritize processing of abort commands.

2. The host bus adapter system of claim 1 wherein:

the first processing path comprises a first register;

the second processing path comprises a second register; and

wherein the selector is configured to select abort commands from the first buffer and I/O commands from the second buffer and is configured to prioritize processing of abort commands.

3. The host bus adapter system of claim 1 wherein:

the first buffer comprises a first ring buffer for queuing abort commands and a first register;

the second buffer comprises a second ring buffer for queuing regular I/O commands and a second register; and

wherein the selector is configured to select abort commands from the first ring buffer and I/O commands from the second ring buffer and is configured to prioritize processing of abort commands.

4. The host bus adapter system of claim 1, wherein:

said first processing path, said second processing path, and said selector for each of said at least 128 channels is implemented in an FPGA.

5. The host bus adapter system of claim 1, wherein the host bus adapter system comprises a fiber channel adapter and a proxy host bus adapter.

6. The host bus adapter system of claim 1 wherein:

the host bus adapter system further comprises a router for receiving regular I/O commands and abort commands and directing said commands to a particular channel of the at least 128 channels and to one of the first processing path and second processing path of said particular channel of the at least 128 channels based on whether the received command is a regular I/O command or an abort command.

7. The host bus adapter system of claim 2, wherein:

said first buffer, said second buffer, said first processing path, said second processing path, and said selector are implemented in hardware.

8. The host bus adapter system of claim 2, wherein:

the first processing path, first buffer, second processing path, second buffer, and selector for each of the at least 128 channels is implemented in an FPGA.

9. The host bus adapter system of claim 2, wherein:

said first buffer, said second buffer, said first processing path, said second processing path, and said selector for each of said 128 channels are implemented in hardware.

10. The host bus adapter system of claim 2, wherein:

said first buffer, said second buffer, said first processing path, said second processing path, and said selector for each of said 128 channels are implemented in hardware; and

wherein the host bus adapter system further comprises a router for receiving regular I/O commands and abort commands and directing said commands to a particular channel of the at least 128 channels and to one of the first processing and second processing path of the particular channel based on whether the received command is a regular I/O command or an abort command.

11. A computer-implemented method for supporting abort processing in a host bus adapter system, the method comprising:

providing at least 128 of channels;

providing, for each of said at least 128 channels, a first processing path for processing abort commands, wherein the first processing path comprises a first buffer for queuing abort commands;

providing, for each of said at least 128 channels, a second processing path for processing regular I/O commands, wherein the second processing path comprises a second buffer for queuing regular I/O commands;

providing, for each of said at least 128 channels, a selector for selecting commands to be processed;

routing, for each of said at least 128 channels, received commands to the first processing path if they are abort commands and to the second processing path if they are regular I/O commands;

whereby, for each of said at least 128 channels, abort commands and regular I/O commands are processed in parallel and the selector is configured to prioritize processing of abort commands.

12. The method of claim 11 wherein:

providing, for each of said at least 128 channels, a first register associated with the first buffer for queuing abort commands;

providing, for each of said at least 128 channels, a second register associated with the second buffer for queuing regular I/O commands; and

wherein the method further comprises, for each of said at least 128 channels, selecting abort commands from the first buffer and I/O commands from the second buffer using the selector to prioritize processing of abort commands.

13. The method of claim 11 wherein:

said first buffer is a first ring buffer and said second buffer is a second ring buffer.

14. The method of claim 11, wherein providing, for each of said at least 128 channels, the first processing path, the second processing path, and the selector comprises:

configuring an FPGA to provide, for each of said at least 128 channels, the first processing path, the second processing path, and the selector.

15. The method of claim 11, further comprising:

providing the host bus adapter system with a fiber channel adapter and a proxy host bus adapter.

16. The method of claim 11 further comprising:

providing a router for receiving regular I/O commands and abort commands and directing said commands to a particular channel of said at least 128 channels and to one of the first processing and second processing path based on whether the received command is a regular I/O command or an abort command.

17. The method of claim 12, further comprising:

providing, for each of the at least 128 channels, a first register for storing a next abort command position in said first buffer and a second register for storing a next regular I/O command position in said second buffer.

18. The method of claim 11, further comprising:

providing, for each of the at least 128 channels, a first register for storing a next abort command position in said first buffer and a second register for storing a next regular I/O command position in said second buffer; and

providing a scheduling selector which schedules commands in a round robin fashion for all of said at least 128 channels.

19. The method of claim 11, wherein providing, for each of said at least 128 channels, a selector for selecting commands to be processed comprises:

providing, for each of said at least 128 channels, a two to one priority scheduling mux for selecting commands to be processed from the first buffer and the second buffer.

20. A non-transitory computer-readable storage medium having stored thereon for supporting abort processing in a host bus adapter system, which instructions, when executed cause the host bus adapter system to perform steps comprising:

providing at least 128 of channels;

providing, for each of said at least 128 channels, a first processing path for processing abort commands, wherein the first processing path comprises a first buffer for queuing abort commands;

providing, for each of said at least 128 channels, a second processing path for processing regular I/O commands, wherein the second processing path comprises a second buffer for queuing regular I/O commands;

providing, for each of said at least 128 channels, a selector for selecting commands to be processed;

routing, for each of said at least 128 channels, received commands to the first processing path if they are abort commands and to the second processing path if they are regular I/O commands;

whereby, for each of said at least 128 channels, abort commands and regular I/O commands are processed in parallel and the selector is configured to prioritize processing of abort commands.