Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate

• US 10,424,668 B2
• Filed: 03/02/2018
• Issued: 09/24/2019
• Est. Priority Date: 09/20/2017
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Ltd.
• Original Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Ltd.
• Inventors: Li, Songshan
• Primary Examiner(s): Woldegeorgis, Ermias T
• Application Number:
  US15/910,264
• Publication Number:
  US 20190088787A1
• Time in Patent Office: 571 Days
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 21/38 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu²⁺, Al³⁺, Mg²⁺, Zn²⁺ and Ni²⁺. A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.

Claims

1. A method of forming a low temperature polysilicon thin film transistor (LTPS TFT), comprising:

providing a substrate;

forming a buffer layer, a low temperature polysilicon layer, a source contact area to be formed, a drain contact area to be formed, a gate insulating layer and a gate layer on the substrate successively;

wherein the source contact area to be formed and the drain contact area to be formed are disposed in a same layer with the low temperature polysilicon layer and at two opposite sides of the low temperature polysilicon layer separately;

depositing an insulation metal oxide layer on the low temperature polysilicon layer to cover the source contact area to be formed and the drain contact area to be formed, and driving individually metal ions of the insulation metal oxide layer into the source contact area to be formed and the drain contact area to be formed to form the source contact area and the drain contact area after an annealing procedure;

wherein the metal ions include at least one of Cu2+, Al3+, Mg2+, Zn2+ and Ni2+; and

forming a source contacting the source contact area and a drain contacting the drain contact area on the low temperature polysilicon layer.

2. The method of forming the LTPS TFT according to claim 1, wherein a temperature of the annealing procedure is about 300-450°

C. and a period of the annealing procedure is 30-50 min.

3. The method of forming the LTPS TFT according to claim 1, wherein a material of the insulation metal oxide layer includes at least one of CuO, Al2O3, MgO, ZnO and NiO.

4. The method of forming the LTPS TFT according to claim 1, wherein a thickness of the insulation metal oxide layer is about 10-20 nm.

5. The method of forming the LTPS TFT according to claim 1, further comprising:

depositing a dielectric layer on the gate layer to cover the gate layer and the insulation metal oxide layer before forming the source and the drain;

performing a dry etching to form a first contact hole and a second contact hole passing through the dielectric layer and the insulation metal oxide layer, for exposing the source contact area and the drain contact area separately; and

forming the source connecting with the source contact area through the first contact hole and the drain connecting with the drain contact area through the second contact hole on the dielectric layer.

6. The method of forming the LTPS TFT according to claim 1, further comprising:

removing the annealed insulation metal oxide layer by a dry etching before forming the source and the drain;

depositing a dielectric layer on the gate layer to cover the gate layer, the low temperature polysilicon layer and the buffer layer;

performing a dry etching to form a third contact hole and a fourth contact hole passing through the dielectric layer, for exposing the source contact area and the drain contact area separately; and

forming the source connecting with the source contact area through the third contact hole and the drain connecting with the drain contact area through the fourth contact hole on the dielectric layer.

7. The method of forming the LTPS TFT according to claim 1, wherein a physical vapor deposition (PVD) process is applied to form the insulation metal oxide layer, and the PVD process includes applying an inert gas at a flow of 2-6 sccm, wherein a pressure of the inert gas is 0.2-1.0 Pa, and a deposition power of the PVD process is 10-15 kw.