High current, low equivalent series resistance printed circuit board coil for power transfer application

• US 10,431,372 B2
• Filed: 10/05/2017
• Issued: 10/01/2019
• Est. Priority Date: 02/20/2012
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Zabaco, Jorge
• Primary Examiner(s): Le, Dinh T
• Application Number:
  US15/725,530
• Publication Number:
  US 20180047495A1
• Time in Patent Office: 726 Days
• Field of Search: 307104
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Claims

1. A device, comprising:

a housing; and

a wireless charging coil, the coil including a layered structure of electric conductors on a printed circuit board (PCB), wherein the layered structure comprises;

a first layer including a first electrically conductive trace comprising a first turn and a second turn adjacent to the first turn;

a second layer including a second electrically conductive trace comprising a third turn and a fourth turn adjacent to the third turn; and

a plurality of vias coupling the first layer and the second layer, wherein the plurality of the vias include a first via, a second via and a third via distributed separately along a length of the first turn, each of the first via, the second via and the third via electrically connecting the first turn and the third turn, wherein the plurality of the vias further include a fourth via, a fifth via and sixth via distributed separately along a length of the second turn, each of the fourth via, fifth via and sixth via connecting the second turn and the fourth turn, wherein thickness of the device is less than 1 centimeter.

2. The device of claim 1, wherein the first electrically conductive trace is surrounded by one or more non-conductive materials.

3. The device of claim 1, wherein the first electrically conductive trace, the second electrically conductive trace and the vias comprise a common material.

4. The device of claim 1, further comprising one or more other circuit components integrated with the first layer and the second layer on the PCB.

5. The device of claim 1, wherein the vias are formed in a cylindrical shape positioned vertically to the first layer and the second layer.

6. The device of claim 1, wherein at least some of the vias have different sizes.

7. The device of claim 1, wherein the first via is adjacent to the second via and the second via is adjacent to the third via, wherein distance between the first via and the second via is different from distance between the second via and the third via.

8. The device of claim 1, wherein cross sections of the first via, the second via and the third via are round shaped.

9. The device of claim 1, wherein the second layer is on the PCB.

10. The device of claim 1, wherein the first via, the second via and the third via are positioned for low equivalent series resistance of the layered structure of electric conductors.

11. The device of claim 1, wherein the electrically conductive trace is etched from a copper sheet laminated onto the PCB.

12. The device of claim 1, wherein thickness of the electrically conductive trace is about 25 micrometers.

13. The device of claim 1, wherein the second via is positioned between the first via and the third via along the length of the first turn.

14. The device of claim 1, wherein the device is a smartphone.

15. The device of claim 1, wherein the device further comprises a touchscreen.

16. The device of claim 1, wherein the device further comprises a microphone and a speaker.

17. The device of claim 1, wherein the device further comprises a front camera.