Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays

• US 10,431,596 B2
• Filed: 08/27/2018
• Issued: 10/01/2019
• Est. Priority Date: 08/28/2017
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Herner, Scott Brad, Harari, Eli
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US16/113,296
• Publication Number:
  US 20190067327A1
• Time in Patent Office: 400 Days
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a planar surface;

an array of memory cells sharing a common bit line that extends along a first direction substantially parallel the planar surface of the semiconductor substrate, wherein a first group of the memory cells are provided on a first side of the common bit line and wherein a second group of the memory cells are provided on a second side of the common bit line opposite the first side and wherein each memory cell comprises a storage layer;

a first plurality of conductors provided above the semiconductor substrate and below the array of memory cells, each conductor in the first plurality of conductors extending along a second direction that is parallel the planar surface and substantially perpendicular to the first direction, wherein the conductors of the first plurality of conductors are separated from each other by a first distance;

a second plurality of conductors provided above the array of memory cells, each conductor in the second plurality of conductors extending along the second direction, wherein the conductors of the second plurality of conductors are separated from each other by the first distance, and wherein the second plurality of conductors are offset from the first set of conductors by substantially half the first distance along the first direction;

a third plurality of conductors each extending along a third direction substantially perpendicular to the planar surface, wherein a first group of the third plurality of conductors each contact a conductor in the first plurality of conductors and wherein a second group of the third plurality of conductors each contact a conductor in the second plurality of conductors, wherein each conductor in the first and second groups of the third plurality of conductors are provided in contact with a storage layer of a memory cell in the first group or the second group of the memory cells, serving as a gate electrode for the memory cell.

2. The memory structure of claim 1, wherein the memory cells share a common source line.

3. The memory structure of claim 1, wherein circuitry is formed in or on the semiconductor substrate, wherein each of the first and second pluralities of conductors and the common bit line are electrically connected to the circuitry.

4. The memory structure of claim 1, wherein the conductors in the first and second pluralities of conductors comprise metal conductors.

5. The memory structure of claim 1, wherein the conductors in the third plurality of conductors comprise polysilicon.

6. The memory structure of claim 2, wherein the common source line is isolated from the circuitry except when pre-charged to a predetermined voltage through the common bit line.

7. The memory structure of claim 1, wherein each memory cell stores more than one bit of information.

8. The memory structure of claim 6, wherein each memory cell stores more than one bit of information.