Array substrate, display panel, and display apparatus

• US 10,431,602 B2
• Filed: 06/07/2017
• Issued: 10/01/2019
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Tian, Lu
• Primary Examiner(s): Arora, Ajay
• Application Number:
  US15/572,090
• Publication Number:
  US 20180350840A1
• Time in Patent Office: 846 Days
• Field of Search: 257 72
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/28 Adhesive materials or arrangements
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

An array substrate is disclosed herein, which includes a display area and a surrounding area. The surrounding area encircles the display area, and includes a first zone and a second zone. The first zone and the second zone are configured to have a height difference to form a substantially uneven upper surface of the array substrate to thereby allow a sealant to be securely attached onto the array substrate. The array substrate further includes a substrate, a first signal line, and a second signal line. The first signal line is disposed over the substrate. The second signal line is disposed over, insulated from, and staggered at a staggering region with, the first signal line. It is configures such that the staggering region is in the first zone. A display panel and a display apparatus containing the array substrate is further disclosed.

Claims

1. An array substrate, comprising:

a display area; and

a surrounding area having a first signal line, and a second signal line disposed over, insulated from, and staggered at a staggering region with, the first signal line, the surrounding area encircling the display area;

wherein;

the surrounding area comprises a first zone and a second zone, wherein the first zone and the second zone are configured to have a height difference to form a substantially uneven upper surface of the array substrate to thereby allow a sealant to be securely attached onto the array substrate; and

an upper surface of the first zone is substantially flat across the first zone from over a side of the second signal line to an opposing side of the second signal line.

2. The array substrate of claim 1, further comprising:

a substrate;

wherein;

the first signal line is disposed over the substrate; and

the second signal line has a substantially flat upper surface across the second signal line;

wherein;

the staggering region is in the first zone; and

an orthographic projection of the first signal line on the substrate crosses an orthographic projection of the second signal line on the substrate at a region coinciding with an orthographic projection of the staggering region on the substrate.

3. The array substrate of claim 2, further comprising an insulating layer, disposed between the first signal line and the second signal line at the staggering region.

4. The array substrate of claim 2, further comprising a separation layer, disposed between the insulating layer and the second signal line at the staggering region.

5. The array substrate of claim 3, further comprising at least one thin-film transistor (TFT), each having a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode, successively disposed over the substrate, wherein:

the first signal line and the gate electrode are configured to be at a substantially same layer and have a substantially same composition;

the insulating layer and the gate insulating layer are configured to be at a substantially same layer and have a substantially same composition;

the separation layer and the semiconductor active layer are configured to be at a substantially same layer and have a substantially same composition; and

the second signal line and the source electrode and the drain electrode are configured to be at a substantially same layer and have a substantially same composition.

6. The array substrate of claim 1, further comprising at least one insulating material layer, disposed over an upper surface of the first zone and the second zone of the surrounding area, wherein the at least one insulating material layer has a thickness in the first zone lower than in the second zone.

7. The array substrate of claim 1, further comprising at least one insulating material layer, disposed over an upper surface of the second zone of the surrounding area.

8. The array substrate of claim 2, further comprising at least one insulating material layer, disposed over an upper surface of the staggering region in the first zone and the second zone, wherein the at least one insulating material layer has a thickness in the staggering region lower than in the second zone.

9. The array substrate of claim 6, wherein the at least one insulating material layer comprises a resin layer.

10. The array substrate of claim 9, wherein the resin layer has a dielectric constant of substantially 1 to 4.

11. The array substrate of claim 9, wherein the at least one insulating material layer further comprises a protection layer, wherein the protection layer is disposed over the resin layer.

12. The array substrate of claim 11, wherein the protection layer comprises SiN_x.

13. The array substrate of claim 2, wherein a height of the first zone is measured from the upper surface of the first zone in contact with the sealant to a bottom surface of the substrate distal from the first signal line;

and a height of the second zone is measured from an upper most surface of the second zone in contact with the sealant to the bottom surface of the substrate distal from the first signal line.

14. The array substrate of claim 1, wherein an upper surface of the second zone of the surrounding area is uneven.

15. A display panel, comprising the array substrate according to claim 1.

16. The display panel according to claim 15, further comprising:

an opposite substrate; and

a sealant;

wherein;

the sealant is disposed between the array substrate and the opposite substrate; and

the sealant is configured to securely attach the array substrate in the first zone and the second zone in the surrounding area of the array substrate.

17. A display apparatus, comprising the display panel according to claim 15.

18. The array substrate of claim 2, wherein the upper surface of the first zone is substantially flat throughout over the staggering region and over the first and second signal lines.

19. The array substrate of claim 1, wherein the first zone is closer to the display area than the second zone.