Control circuit for synchronous rectifier and the method thereof

CAFC
  • US 10,432,104 B2
  • Filed: 06/28/2018
  • Issued: 10/01/2019
  • Est. Priority Date: 07/11/2017
  • Status: Active Grant
First Claim
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1. A synchronous switching converter comprising:

  • an energy storage component;

    a synchronous rectifier coupled to the energy storage component;

    a secondary control circuit configured to receive a slew rate threshold adjusting signal and a voltage across the synchronous rectifier, and to provide a secondary control signal based on the slew rate threshold adjusting signal and the voltage across the synchronous rectifier to control the synchronous rectifier; and

    an off-chip component configured to provide the slew rate threshold adjusting signal;

    wherein the secondary control circuit detects a slew rate of the voltage across the synchronous rectifier, and maintains the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold;

    wherein the secondary control circuit comprises;

    a first comparator having a first input terminal configured to receive a first threshold, a second input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide a first comparison signal based on a comparison result of the voltage across the synchronous rectifier with the first threshold;

    a second comparator having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive a second threshold, and an output terminal configured to provide a second comparison signal based on a comparison result of the voltage across the synchronous rectifier with the second threshold;

    a pulse circuit having an input terminal configured to receive the first comparison signal, an adjusting terminal configured to receive the slew rate threshold adjusting signal, and an output terminal configured to provide a pulse signal based on the first comparison signal and the slew rate threshold adjusting signal, wherein when the first comparison signal flips from a second voltage level to a first voltage level, the pulse signal has a pulse maintaining a time period, and wherein the time period could be adjusted by the slew rate threshold adjusting signal; and

    a logic gate circuit having a first input terminal configured to receive the pulse signal, a second input terminal configured to receive the second comparison signal, and an output terminal configured to provide the on control signal based on a logic operation to the pulse signal and the second comparison signal.

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