Dynamic core selection for heterogeneous multi-core systems

• US 10,437,318 B2
• Filed: 01/02/2016
• Issued: 10/08/2019
• Est. Priority Date: 03/11/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Youfeng, Hu, Shiliang, Borin, Edson, Wang, Cheng
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US14/986,677
• Publication Number:
  US 20160116964A1
• Time in Patent Office: 1,375 Days
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3452 Performance evaluation by statistical analysis
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/865 Monitoring of software
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Claims

1. An apparatus for multi-core processing, the apparatus comprising:

a memory controller;

a first processor core of a first type to execute program code;

a second processor core of a second type different from the first type; and

a code distribution module to determine a performance metric of execution of the program code by the first processor core, determine a performance metric of the second processor core indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function, and switch execution of the program code from the first processor core to the second processor core in response to a determination that the performance metric of the second processor core is better than the performance metric of the first processor core or continue execution of the program code with the first processor core in response to a determination that the performance metric of the second processor core is not better than the performance metric of the first processor core.

2. The apparatus of claim 1, further comprising an integrated circuit that includes the memory controller, the first processor core, the second processor core, and the code distribution module.

3. The apparatus of claim 1, wherein the code distribution module is further to determine an amount of power consumed during execution of a code region.

4. The apparatus of claim 1, wherein the code distribution module is further to power down the first processor core in response to a switch in execution of the program code from the first processor core to the second processor core.

5. The apparatus of claim 1, wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

6. The apparatus of claim 1, wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

7. The apparatus of claim 1, wherein the memory controller is to manage a memory shared by the first processor core and the second processor core.

8. A method for processing by a multi-core processing system, the method comprising:

executing program code on a first processor core of the multi-core processing system;

determining a performance metric of execution of the program code by the first processor core;

determining a performance metric of a second processor core of the multi-core processing system indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function and wherein the first processor core is of a first type and the second processor core is of a second type different from the first type; and

switching execution of the program code from the first processor core to the second processor core in response to determining that the performance metric of the second processor core is better than the performance metric of the first processor core or continuing execution of the program code with the first processor core in response to a determination that the performance metric of the second processor core is not better than the performance metric of the first processor core.

9. The method of claim 8, wherein the multi-core processing system is an integrated circuit that includes the first processor core, the second processor core, and a memory controller to manage a memory shared by the first processor core and the second processor core.

10. The method of claim 8, further comprising determining an amount of power consumed during execution of a code region.

11. The method of claim 8, further comprising powering down the first processor core in response to switching execution of the program code from the first processor core to the second processor core.

12. The method of claim 8, wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

13. The method of claim 8, wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

14. One or more non-transitory machine-readable storage media comprising a plurality of instructions embodied thereon that, in response to execution by one or more processors of a multi-core processing system, causes the one or more processors to:

execute program code on a first processor core of the multi-core processing system;

determine a performance metric of execution of the program code by the first processor core;

determine a performance metric of a second processor core of the multi-core processing system indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function and wherein the first processor core is of a first type and the second processor core is of a second type different from the first type; and

switch execution of the program code from the first processor core to the second processor core in response to a determination that the performance metric of the second processor core is better than the performance metric of the first processor core or continue execution of the program code with the first processor core in response to a determination that the performance metric of the second processor is not better than the performance metric of the first processor core.

15. The one or more non-transitory machine-readable storage media of claim 14, wherein the multi-core processing system is an integrated circuit that includes the first processor core, the second processor core, and a memory controller to manage a memory shared by the first processor core and the second processor core.

16. The one or more non-transitory machine-readable storage media of claim 14, wherein the plurality of instructions further causes the one or more processors to determine an amount of power consumed during execution of a code region.

17. The one or more non-transitory machine-readable storage media of claim 14, wherein the plurality of instructions further causes the one or more processors to power down the first processor core in response to a switch in execution of the program code from the first processor core to the second processor core.

18. The one or more non-transitory machine-readable storage media of claim 14, wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

19. The one or more non-transitory machine-readable storage media of claim 14, wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.