Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
First Claim
1. A method of writing data into a memory device, the method comprising:
- utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;
writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;
detecting a power down signal;
responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and
powering down the memory device.
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Abstract
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from the cache memory into a secure memory storage area reserved in the memory bank. Finally, the method comprises powering down the memory device.
493 Citations
20 Claims
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1. A method of writing data into a memory device, the method comprising:
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utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank; writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; detecting a power down signal; responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and powering down the memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device for storing data, the memory device comprising:
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a memory bank comprising a plurality of addressable memory cells; a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank; a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and a logic module operable to; detect a power down signal; responsive to the power down signal, transfer the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and power down the memory device. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A memory device for storing data, the memory device comprising:
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a memory bank comprising a plurality of addressable memory cells; a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank; a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and a logic module operable to; detect a power up signal; responsive to the power up signal, transfer the second plurality of data words and associated memory addresses from said a secure memory storage area to said cache memory; and cause said pipeline to process said second plurality of data words, from said cache memory, for writing into said memory bank. - View Dependent Claims (18, 19, 20)
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Specification