Apparatuses and methods for maintaining a duty cycle error counter
First Claim
1. An apparatus comprising:
- a counter, wherein the counter is configured to;
encode a first value to a second value, wherein the first value is represented by a binary code and the second value is represented by a Gray code,count up or count down the second value by a specified step to output a third value, wherein the third value is represented by the Gray code, anddecode the third value to a fourth value with masking a part of the fourth value responsive to a control signal, wherein the fourth value is represented by the binary code.
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Accused Products
Abstract
Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.
62 Citations
19 Claims
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1. An apparatus comprising:
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a counter, wherein the counter is configured to; encode a first value to a second value, wherein the first value is represented by a binary code and the second value is represented by a Gray code, count up or count down the second value by a specified step to output a third value, wherein the third value is represented by the Gray code, and decode the third value to a fourth value with masking a part of the fourth value responsive to a control signal, wherein the fourth value is represented by the binary code. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus comprising:
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a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal, the duty cycle detect circuit including a counter configured to store a count value indicating the duty cycle error using Gray code, wherein the counter is adjusted in response to detection of non-zero duty cycle error and the counter is further configured to convert the count value from Gray code to binary code as a binary count value, wherein the duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value; and a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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receiving a clock signal; detecting a duty cycle error of the clock signal; storing a count value indicating the duty cycle error using Gray code; in response to detecting a non-zero duty cycle error, adjusting the count value by a step size; converting the count value from Gray code to binary code to provide a binary count value; providing a duty cycle error signal based on the binary count value; and adjusting a duty cycle of the clock signal based on the duty cycle error signal. - View Dependent Claims (16, 17, 18, 19)
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Specification