Memory devices and methods of writing memory cells at different moments in time

• US 10,438,661 B2
• Filed: 05/23/2016
• Issued: 10/08/2019
• Est. Priority Date: 06/10/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Otsuka, Wataru, Kunihiro, Takafumi, Tsushima, Tomohito, Kitagawa, Makoto, Sumino, Jun
• Primary Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US15/162,420
• Publication Number:
  US 20160267978A1
• Time in Patent Office: 1,233 Days
• Field of Search: 365148, 365163
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/0085 Write a page or sector of information simultaneously, e.g. a complete row or word line
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Claims

1. A memory system comprising:

a common conductor;

a plurality of memory cells coupled with the common conductor;

access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time;

wherein the access circuitry is configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state;

wherein the memory cells have memory elements which individually have different electrical resistances which correspond to the different memory states;

wherein the memory cells have a decreased electrical resistance in the one memory state compared with another of the memory states; and

wherein the access circuitry is configured to maintain the common conductor at the voltage potential which is an increased voltage potential compared with another voltage potential which is applied to the memory cells between the first and second moments in time.

2. The memory system of claim 1 wherein the common conductor is adjacent to one side of the memory elements of the memory cells which is opposite to another side of the memory elements which are coupled with a plurality of bit lines.

3. The memory system of claim 1 wherein all of the memory cells which are coupled with the common conductor are provided in the one memory state between the first and second moments in time.

4. The memory system of claim 1 wherein the memory cells are non-volatile memory cells.

5. The memory system of claim 1 wherein the common conductor comprises first electrodes of the memory cells, and the access circuitry is configured to provide the another voltage potential corresponding to the one memory state to second electrodes of the different memory cells at the different moments in time.

6. The memory system of claim 5 wherein the maintaining the common conductor at the increased voltage potential and the provision of the another voltage potential to the second electrodes forms conductive structures between the first and second electrodes of the memory cells.

7. The memory system of claim 1 wherein the access circuitry is configured to assert different word lines which are coupled with the different ones of the memory cells at the different moments in time between the first and second moments in time.

8. The memory system of claim 1 wherein the common conductor comprises an electrode of each of the memory cells.

9. A memory writing method comprising:

applying a first voltage potential to a common conductor which is coupled with a plurality of memory cells;

with the first voltage potential continuously applied to the common conductor, asserting different word lines which are coupled with different ones of the memory cells at different moments in time;

during the asserting of an individual one of the word lines, applying a second voltage potential to the memory cells which are coupled with the asserted individual word line; and

wherein the applyings of the first and second voltage potentials to the memory cells which are coupled with the asserted individual word line write the memory cells which are coupled with the asserted individual word line to one of a plurality of different memory states.

10. The method of claim 9 wherein the applyings write all of the memory cells which are coupled with the asserted individual word line to the one memory state.

11. The method of claim 9 wherein the applyings change an electrical resistance of the memory cells which are coupled with the asserted individual word line.

12. The method of claim 9 wherein the applyings one of create and remove conductive structures within the memory cells which are coupled with the asserted individual word line to write the memory cells which are coupled with the asserted individual word line.

13. The method of claim 9 wherein the different moments in time occur between an initial one and a subsequent one of the moments in time, and wherein the applying the first voltage comprises continuously maintaining the common conductor at the first voltage potential during and between the initial and subsequent moments in time.

14. The method of claim 9 wherein the writing the plurality of memory cells comprises writing independent of data.