Pixel unit, array substrate and manufacturing method therefor, display panel and display device
First Claim
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1. A pixel unit, comprising a display region and a thin film transistor (TFT) component region, wherein in the TFT component region, a base, a gate line, a gate insulating layer, an active layer and a data line, a source electrode and a drain electrode, and a pixel electrode lapped onto the drain electrode are provided sequentially from the bottom up,wherein an extension direction of a channel between the source electrode and the drain electrode is perpendicular to a direction oriented from the source electrode to the drain electrode;
- a top surface of the drain electrode has at least four step portions arranged along the extension direction of the channel, and portions of the top surface of the drain electrode at two sides of each of the at least four step portions have different heights relative to a top surface of the gate insulating layer;
wherein the pixel electrode is in contact with each of the at least four step portions of the top surface of the drain electrode at a side of the drain electrode away from the base; and
an arrangement direction of the at least four step portions is parallel to the extension direction of the channel between the source electrode and the drain electrode, wherein the arrangement direction of the at least four step portions is inclined to the base.
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Abstract
Disclosed are a pixel unit, an array substrate and a manufacturing method therefor, a display panel and a display device. At least two step portions adjacent to each other in an upward direction are provided at at least one of a first side of a drain electrode close to a display region and a second side of the drain electrode away from the display region, such that a pixel electrode is lapped onto the drain electrode gently.
9 Citations
16 Claims
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1. A pixel unit, comprising a display region and a thin film transistor (TFT) component region, wherein in the TFT component region, a base, a gate line, a gate insulating layer, an active layer and a data line, a source electrode and a drain electrode, and a pixel electrode lapped onto the drain electrode are provided sequentially from the bottom up,
wherein an extension direction of a channel between the source electrode and the drain electrode is perpendicular to a direction oriented from the source electrode to the drain electrode; -
a top surface of the drain electrode has at least four step portions arranged along the extension direction of the channel, and portions of the top surface of the drain electrode at two sides of each of the at least four step portions have different heights relative to a top surface of the gate insulating layer; wherein the pixel electrode is in contact with each of the at least four step portions of the top surface of the drain electrode at a side of the drain electrode away from the base; and an arrangement direction of the at least four step portions is parallel to the extension direction of the channel between the source electrode and the drain electrode, wherein the arrangement direction of the at least four step portions is inclined to the base. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An array substrate comprising a pixel unit, wherein the pixel unit comprises a display region and a thin film transistor (TFT) component region, in the TFT component region, a base, a gate line, a gate insulating layer, an active layer and a data line, a source electrode and a drain electrode, and a pixel electrode lapped onto the drain electrode are provided sequentially from the bottom up, wherein
an extension direction of a channel between the source electrode and the drain electrode is perpendicular to a direction oriented from the source electrode to the drain electrode; -
a top surface of the drain electrode has at least four step portions arranged along the extension direction of the channel, and portions of the top surface of the drain electrode at two sides of each of the at least four step portions have different heights relative to a top surface of the gate insulating layer; wherein the pixel electrode is in contact with each of the at least four step portions of the top surface of the drain electrode at a side of the drain electrode away from the base; and an arrangement direction of the at least four step portions is parallel to the extension direction of the channel between the source electrode and the drain electrode, wherein the arrangement direction of the at least four step portions is inclined to the base. - View Dependent Claims (12, 13, 14, 15)
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16. A manufacturing method of an array substrate, wherein the array substrate comprises a plurality of pixel units, each of the plurality of pixel units comprises a display region and a thin film transistor (TFT) component region, wherein in the TFT component region, a base, a gate line, a gate insulating layer, an active layer and a data line, a source electrode and a drain electrode, and a pixel electrode lapped onto the drain electrode are provided sequentially from the bottom up, an extension direction of a channel between the source electrode and the drain electrode is perpendicular to a direction oriented from the source electrode to the drain electrode, a top surface of the drain electrode has at least four step portions arranged along the extension direction of the channel and portions of the top surface of the drain electrode at two sides of each of the at least four step portions have different heights relative to a top surface of the gate insulating layer, and the pixel electrode is in contact with each of the at least four step portions of the top surface of the drain electrode at a side of the drain electrode away from the base, and wherein the manufacturing method comprises:
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providing the base, forming a patterned gate line on the base, forming the gate insulating layer on the gate line, and forming the active layer and the data line on the gate insulating layer; forming a patterned source electrode and a patterned drain electrode on the active layer; forming the at least four step portions adjacent to each other in the upward direction at the at least one of the first side of the drain electrode close to the display region and the second side of the drain electrode away from the display region by means of a partially transparent mask plate; and lapping the pixel electrode onto the drain electrode having the step portions gently; wherein an arrangement direction of the at least four step portions is parallel to the extension direction of the channel between the source electrode and the drain electrode, wherein the arrangement direction of the at least four step portions is inclined to the base.
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Specification
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Current AssigneeBeijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
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Original AssigneeBOE Technology Group Co., Ltd.
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InventorsWang, Xiao
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Primary Examiner(s)Hossain, Moazzam
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Assistant Examiner(s)Mojaddedi, Omar F
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Application NumberUS15/135,689Publication NumberTime in Patent Office1,271 DaysField of Search257 72US Class CurrentCPC Class CodesH01L 27/1244 for preventing breakage, pe...H01L 29/41733 for thin film transistors w...
