Semiconductor circuit

• US 10,447,248 B2
• Filed: 10/18/2018
• Issued: 10/15/2019
• Est. Priority Date: 09/01/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min Su
• Primary Examiner(s): Luu, An T
• Application Number:
  US16/164,329
• Publication Number:
  US 20190052249A1
• Time in Patent Office: 362 Days
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Claims

1. A semiconductor circuit comprising:

a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;

a second logic gate that receives inputs of the first input signal and the feedback signal, and performs a second logical operation; and

a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a third logical operation to output the feedback signal, wherein;

the first input signal comprises an enable signal and a scan-enable signal, and the first logic gate comprises a composite logic gate that performs a first sub-logical operation on the enable signal and the scan-enable signal to generate a first intermediate signal, and performs a second sub-logical operation on the first intermediate signal, the clock signal and the feedback signal to output the first output signal, or

the first input signal comprises a second input signal and the scan-enable signal, and the first logic gate comprises a composite logic gate that performs a first sub-logical operation on the second input signal and the scan-enable signal to generate a first intermediate signal, and performs a second sub-logical operation on the first intermediate signal, the clock signal and the feedback signal to output the first output signal.

2. The semiconductor circuit of claim 1, when the first input signal comprises the enable signal and the scan-enable signal, wherein:

each of the first sub-logical operation and the second sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the first sub-logical operation and the second sub-logical operation is respectively an AND logical operation and a NOR logical operation.

3. The semiconductor circuit of claim 1, when the first input signal comprises the enable signal and the scan-enable signal, wherein the second logic gate comprises a composite logic gate that performs a third sub-logical operation on the enable signal and the scan-enable signal to generate a second intermediate signal, and performs a fourth sub-logical operation on the second intermediate signal and the feedback signal.

4. The semiconductor circuit of claim 3, wherein:

each of the third sub-logical operation and the fourth sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the third sub-logical operation and the fourth sub-logical operation is respectively an AND logical operation and a NOR logical operation.

5. The semiconductor circuit of claim 1, when the first input signal comprises the second input signal and the scan-enable signal, wherein:

each of the first sub-logical operation and the second sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the first sub-logical operation and the second sub-logical operation is respectively an AND logical operation and a NOR logical operation.

6. The semiconductor circuit of claim 1, when the first input signal comprises the second input signal and the scan-enable signal, wherein the second logic gate performs a third sub-logical operation on the second input signal and the scan-enable signal to generate a second intermediate signal, and performs a fourth sub-logical operation on the second intermediate signal and the feedback signal.

7. The semiconductor circuit of claim 6 wherein:

each of the third sub-logical operation and the fourth sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the third sub-logical operation and the fourth sub-logical operation is respectively an AND logical operation and a NOR logical operation.

8. The semiconductor circuit of claim 7, further comprising a third logic gate, wherein:

the third logic gate performs a fifth sub-logical operation on the clock signal and an output signal of the second logic gate to generate a third intermediate signal,

performs a sixth sub-logical operation on the scan-enable signal and an inverted signal of a scan input signal to generate a fourth intermediate signal,

performs a seventh sub-logical operation on the third intermediate signal and the fourth intermediate signal to generate a fifth intermediate signal, and

performs an eighth sub-logical operation on the first output signal and the fifth intermediate signal to output the feedback signal.

9. The semiconductor circuit of claim 8, wherein:

each of the fifth sub-logical operation through the eighth sub-logical operation is respectively an AND logical operation, an AND logical operation, an OR logical operation and a NAND logical operation, or

each of the fifth sub-logical operation through the eighth sub-logical operation is respectively an OR logical operation, an OR logical operation, an AND logical operation and a NOR logical operation.

10. A semiconductor circuit comprising:

a first logic gate that outputs a first output signal by receiving inputs of a first input signal, a clock signal, a feedback signal and an inverted signal of the first output signal and performing a first sub-logical operation and a second sub-logical operation;

a second logic gate that receives inputs of the first input signal and the feedback signal to perform a first logical operation; and

a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a second logical operation to output the feedback signal, wherein;

the first input signal comprises an enable signal and a scan-enable signal, and the first logic gate comprises a composite logic gate that performs the first sub-logical operation on the inverted signal of the first output signal, the enable signal and the scan-enable signal to generate a first intermediate signal, and performs the second sub-logical operation on the first intermediate signal, the clock signal and the feedback signal to output the first output signal, or

the first input signal comprises a second input signal and the scan-enable signal, and the first logic gate comprises a composite logic gate that performs the first sub-logical operation on the inverted signal of the first output signal, the second input signal and the scan-enable signal to generate a first intermediate signal, and performs the second sub-logical operation on the first intermediate signal, the clock signal and the feedback signal to output the first output signal.

11. The semiconductor circuit of claim 10, when the first input signal comprises the enable signal and the scan-enable signal, wherein:

each of the first sub-logical operation and the second sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the first sub-logical operation and the second sub-logical operation is respectively an AND logical operation and a NOR logical operation.

12. The semiconductor circuit of claim 10, when the first input signal comprises the enable signal and the scan-enable signal, wherein the second logic gate comprises a composite logic gate that performs a third sub-logical operation on the enable signal and the scan-enable signal to generate a second intermediate signal, and performs a fourth sub-logical operation on the second intermediate signal and the feedback signal.

13. The semiconductor circuit of claim 12, wherein:

each of the third sub-logical operation and the fourth sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the third sub-logical operation and the fourth sub-logical operation is respectively an AND logical operation and a NOR logical operation.

14. The semiconductor circuit of claim 10, further comprising an inverter that receives the input of the first output signal and performs an inversion logical operation to output a second output signal.

15. The semiconductor circuit of claim 10, further comprising:

a latch that receives the inputs of the first output signal and the clock signal to output a third output signal, wherein

the latch comprises a D latch or an R-S latch.

16. The semiconductor circuit of claim 10, the first input signal comprises the second input signal and the scan-enable signal, wherein:

each of the first sub-logical operation and the second sub-logical operation is respectively an OR logical operation and a NAND logical operation, or

each of the first sub-logical operation and the second sub-logical operation is respectively an AND logical operation and a NOR logical operation.

17. The semiconductor circuit of claim 10, the first input signal comprises the second input signal and the scan-enable signal, wherein the second logic gate comprises a composite logic gate that performs a third sub-logical operation on the second input signal and the scan-enable signal to generate a second intermediate signal, and performs a fourth sub-logical operation on the second intermediate signal and the feedback signal.

18. The semiconductor circuit of claim 17, wherein:

each of the third sub-logical operation and the fourth sub-logical operation is an OR logical operation and a NAND logical operation, or

each of the third sub-logical operation and the fourth sub-logical operation is an AND logical operation and a NOR logical operation.

19. The semiconductor circuit of claim 17, wherein:

the third logic gate comprises a composite logic circuit, and

the composite logic circuit performs a fifth sub-logical operation on the clock signal and the output signal of the second logic gate to generate a third intermediate signal,

performs a sixth sub-logical operation on the scan-enable signal and an inverted signal of a scan input signal to generate a fourth intermediate signal,

performs a seventh sub-logical operation on the third intermediate signal and the fourth intermediate signal to generate a fifth intermediate signal, and

performs an eighth sub-logical operation on the first output signal and the fifth intermediate signal to output the feedback signal.

20. The semiconductor circuit of claim 19, wherein:

each of the fifth sub-logical operation through the eighth sub-logical operation is respectively an AND logical operation, an AND logical operation, an OR logical operation and a NAND logical operation, or

each of the fifth sub-logical operation through the eighth sub-logical operation is respectively an OR logical operation, an OR logical operation, an AND logical operation and a NOR logical operation.

21. A semiconductor circuit comprising:

a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;

a second logic gate that receives inputs of the first input signal and the feedback signal, and performs a second logical operation;

a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a third logical operation to output the feedback signal; and

a latch that receives the inputs of the first output signal and the clock signal to output a second output signal, wherein

the latch comprises a D latch or an R-S latch.