Intelligent MSI-X interrupts for video analytics and encoding

• US 10,448,020 B2
• Filed: 04/09/2018
• Issued: 10/15/2019
• Est. Priority Date: 12/28/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doddapuneni, Naveen, Mishra, Animesh, Rodriguez, Jose M.
• Primary Examiner(s): Shyu, Jing-Yih
• Application Number:
  US15/948,068
• Publication Number:
  US 20180227581A1
• Time in Patent Office: 554 Days
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/137 Motion inside a coding unit, e.g. average field, frame or block difference
• CPC Class Codes: H04N 19/20 using video object coding
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/87 involving scene cut or scene change detection in combination with video compression

Abstract

Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.

Claims

1. A method comprising:

generating an interrupt, from an engine to a host, that indicates an interrupt;

providing information as part of the interrupt including address and data values for the interrupt to handle the interrupt; and

sending a single message from the engine to the host including both the interrupt and the information.

2. The method of claim 1 including providing a traffic class for the interrupt.

3. The method of claim 1 including holding off an acknowledge to the interrupt until data transfer to the host is complete.

4. A non-transitory computer readable medium storing instructions executed by a processor to perform a method for encoding multiple video streams in parallel comprising:

generating an interrupt, from an engine to a host, that indicates an interrupt;

providing information as part of the interrupt to handle the interrupt including address and data values for the interrupt; and

sending a single message from the engine to the host including both the interrupt and the information.

5. The medium of claim 4 further storing instructions executed to perform a method including providing a traffic class for the interrupt.

6. The medium of claim 4 further storing instructions executed to perform a method including holding off an acknowledge to the interrupt until data transfer to the host is complete.

7. An apparatus for encoding multiple video streams in parallel comprising:

a video analytics engine; and

an interrupt controller to generate an interrupt, from an engine to a host, that indicates an interrupt, send a single message from the engine to the host including both the interrupt and the information, and said interrupt itself including information as part of the interrupt including address and data values for the interrupt to handle the interrupt.

8. The apparatus of claim 7, said controller to provide a traffic class for the interrupt.

9. The apparatus of claim 7, said controller to hold off an acknowledge to the interrupt until data transfer to the host is complete.