Memory device and operating method thereof

• US 10,452,277 B2
• Filed: 08/29/2016
• Issued: 10/22/2019
• Est. Priority Date: 04/07/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Kwang Su, Shin, Tae Seung
• Primary Examiner(s): Dudek, Jr., Edward J
• Application Number:
  US15/250,856
• Publication Number:
  US 20170293435A1
• Time in Patent Office: 1,149 Days
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present disclosure relates to a memory device and an operating method thereof. A memory device includes an enable signal generation unit generating an enable signal in response to a command; a storage unit storing product information of the memory device; an information generation unit generating variable information of the memory device; and an output unit combining the product information from the storage unit with the variable information from the information generation unit and outputting the combined information in response to the enable signal.

Claims

1. A memory system, comprising:

a memory device storing data;

a memory controller receiving a request from a host, controlling the memory device according to the request, and communicating between the memory device and the host, the memory device comprising;

an enable signal generation unit generating an enable signal in response to a command output from the memory controller;

a fix code storage unit storing product information of the memory device, wherein the product information is not varied;

a logic code generation unit generating variable information of the memory device; and

an output unit combining the product information from the fix code storage unit with the variable information from the logic code generation unit and outputting the combined information in response to the enable signal,

wherein the enable signal generation unit, the fix code storage unit, the logic code generation unit and the output unit are included in a control logic which receives the command from the memory controller and operates the memory device, the output unit being operated in response to a single internal clock used in the control logic for operating the memory device, and

wherein the output unit outputs the combined information using the single internal clock.

2. The memory system of claim 1, wherein the product information does not change regardless of an operation and/or a state of the memory device.

3. The memory system of claim 1, wherein the product information includes at least one of a manufacturing information and a specification information of the memory device.

4. The memory system of claim 1, wherein the product information is stored in the fix code storage unit during a manufacturing process of the memory device.

5. The memory system of claim 1, wherein the variable information includes information varying depending upon an operation and/or a state of the memory device.

6. The memory system of claim 1, wherein the variable information includes at least one of a voltage information about voltages used for various operations performed by the memory device, a cycling number information and bad block information.

7. The memory system of claim 1, wherein the enable signal generation unit outputs the enable signal in response to the command to output the combined information.

8. The memory system of claim 1, wherein the output unit receives the product information and the variable information and outputs the combined information by combining the product information with the variable information in response to the enable signal.

9. The memory system of claim 1, wherein the memory device is a flash memory.

10. A memory device, which stores data and is controlled by a memory controller communicating between the memory device and a host, comprising:

a plurality of memory blocks storing data;

a peripheral circuit performing at least one of a program operation, a read operation and an erase operation on the plurality of memory blocks; and

a control logic controlling the peripheral circuit,

wherein the control logic combines product information, which is not varied, of the memory device with variable information of the memory device in response to a command output from the memory controller, and outputs combined information including the product information and the variable information to the memory controller in response to a single internal clock that is used in the control logic for operating the memory device.

11. The memory device of claim 10, wherein the control logic comprises:

an enable signal generation unit generating the enable signal in response to the command;

a fix code storage unit storing the product information;

a logic code generation unit generating a logic code; and

an output unit combining the product information with the variable information and outputting the combined information in response to the enable signal.

12. The memory device of claim 10, wherein the product information does not change regardless of an operation and a state of the memory device and includes at least one of manufacturing information and specification information of the memory device.

13. The memory device of claim 10, wherein the product information is stored in the control logic during a manufacturing process of the memory device.

14. The memory device of claim 10, wherein the variable information includes one information varying depending on an operation and/or a state of the memory device.

15. The memory device of claim 10, wherein the variable information includes at least one of a voltage information about voltages used for various operations performed by the memory device, cycling number information, and bad block information.

16. A method of operating a memory device, which stores data and is controlled by a memory controller communicating between the memory device and a host, the method comprising:

storing product information of the memory device, wherein the product information is not varied;

generating variable information of the memory device;

generating read information by combining the product information with the variable information; and

outputting the combined information in response to a single internal clock of the memory device, wherein the single internal clock is used in a control logic for operating the memory device.

17. The method of claim 16, wherein the product information is maintained regardless of an operation and/or a state of the memory device, and the variable information is updated by an operation of the memory device.

18. The method of claim 16, wherein the product information includes at least one of a manufacturing information and a specification information of the memory device, and

wherein the variable information includes at least one of voltage information about voltages used for various operations performed by the memory device, cycling number information, and bad block information.