NAND flash memory device
First Claim
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1. A NAND flash memory device comprising:
- an interface circuit configured to communicate with an outside;
a first memory cell array and a second memory cell array, each of which includes a memory cell transistor configured to store data and from each of which data is read for each page unit;
a first register configured to store data read from the first memory cell array;
a second register configured to store data read from the second memory cell array; and
a detection circuit configured to detect an error in data read from the first memory cell array and the second memory cell array,wherein the read data of a size corresponding to the page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided, andwhen performing an operation of outputting the read data, the interface circuit is configured to output information based on the error detected in the read data output during the operation, the operation including at least one of a first operation, a second operation, and a third operation,the first operation concurrently executing;
outputting first data stored in the first register to the outside; and
reading second data different from the first data from the first memory cell array and storing the second data in the first register;
the second operation concurrently executing;
outputting the first data stored in the first register to the outside; and
outputting third data stored in the second register to the outside; and
the third operation concurrently executing;
outputting the first data stored in the first register to the outside;
reading the second data from the first memory cell array and storing the second data in the first register;
outputting the third data stored in the second register to the outside; and
reading fourth data different from the third data from the second memory cell array and storing the fourth data in the second register.
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Abstract
According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.
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Citations
10 Claims
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1. A NAND flash memory device comprising:
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an interface circuit configured to communicate with an outside; a first memory cell array and a second memory cell array, each of which includes a memory cell transistor configured to store data and from each of which data is read for each page unit; a first register configured to store data read from the first memory cell array; a second register configured to store data read from the second memory cell array; and a detection circuit configured to detect an error in data read from the first memory cell array and the second memory cell array, wherein the read data of a size corresponding to the page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided, and when performing an operation of outputting the read data, the interface circuit is configured to output information based on the error detected in the read data output during the operation, the operation including at least one of a first operation, a second operation, and a third operation, the first operation concurrently executing; outputting first data stored in the first register to the outside; and reading second data different from the first data from the first memory cell array and storing the second data in the first register; the second operation concurrently executing; outputting the first data stored in the first register to the outside; and outputting third data stored in the second register to the outside; and the third operation concurrently executing; outputting the first data stored in the first register to the outside; reading the second data from the first memory cell array and storing the second data in the first register; outputting the third data stored in the second register to the outside; and reading fourth data different from the third data from the second memory cell array and storing the fourth data in the second register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification