Nonvolatile logic memory for computing module reconfiguration

• US 10,452,594 B2
• Filed: 10/20/2015
• Issued: 10/22/2019
• Est. Priority Date: 10/20/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Waechter, Andreas, Jung, Mark, Bartling, Steven Craig, Khanna, Sudhanshu
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Bartels, Christopher A
• Application Number:
  US14/887,885
• Publication Number:
  US 20170109054A1
• Time in Patent Office: 1,463 Days
• Field of Search: None
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: H04L 67/303 Terminal profiles

Abstract

Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Claims

1. A computing device apparatus comprising:

computing components that includes two or more device modules of the computing device apparatus, two or more peripherals associated with the computing device apparatus, or at least one device module of the computing device apparatus and at least one peripheral associated with the computing device apparatus;

configuration registers configured to store configuration profile data for currently active settings of the computing components, wherein each computing component contains at least one of the configuration registers;

a system bus;

one or more non-volatile logic arrays configured to store a plurality of configuration profiles for individual settings of the computing components;

a dedicated bus separate from the system bus and connecting the one or more non-volatile logic arrays and the configuration registers, the dedicated bus being coupled in common to the configuration registers;

a non-volatile logic array controller configured to control the one or more non-volatile logic arrays, receive a trigger and, in response to the trigger, control transfer of at least one of the plurality of configuration profiles to associated ones of the configuration registers, wherein the non-volatile logic array controller is configured to transfer at least one of the plurality of configuration profiles to associated ones of the configuration registers using a sub-system clock for a non-volatile logic sub-system for the one or more non-volatile logic arrays, the sub-system clock operating at a different clock speed than a system clock of the computing device apparatus; and

a non-volatile array output multiplexer arranged to selectively couple individual rows of the one or more non-volatile logic arrays to the dedicated bus so that a configuration profile stored in a selected one of the individual rows can be transferred to an associated one of the configuration registers over the dedicated bus, wherein each of the individual rows of the one or more non-volatile logic arrays is coupled to a respective input of the non-volatile array output multiplexer, and wherein the dedicated bus is coupled to an output of the non-volatile array output multiplexer.

2. The computing device apparatus of claim 1, wherein the computing device apparatus is configured to generate the trigger as either or both of a software trigger or a hardware trigger.

3. The computing device apparatus of claim 1, wherein the non-volatile logic array controller is configured to receive a plurality of different triggers, wherein individual ones of the plurality of triggers effects transfer of different ones of the plurality of configuration profiles to associated ones of the configuration registers.

4. The computing device apparatus of claim 3, wherein the computing device apparatus is configured to be modifiable by a user to customize the plurality of the different triggers and associated transfer of the configuration profiles.

5. The computing device apparatus of claim 3, wherein the one or more non-volatile logic arrays are configured to store device module identifier information or peripheral identifier information for individual ones of the plurality of configuration profiles.

6. The computing device apparatus of claim 1, further comprising a non-volatile logic array input multiplexer disposed to selectively connect via the system bus individual ones of the peripherals or computing device modules to individual rows of the one or more non-volatile logic arrays.

7. The computing device apparatus of claim 1, wherein the non-volatile logic array controller and the one or more non-volatile logic arrays are dedicated solely to storage and transfer of the configuration profiles.

8. The computing device apparatus of claim 1, wherein the clock speed of the sub-system clock of the non-volatile logic sub-system is faster than the system clock of the computing device.

9. A computing device apparatus comprising:

computing components that includes two or more device modules of the computing device apparatus, two or more peripherals associated with the computing device apparatus, or at least one device module of the computing device apparatus and at least one peripheral associated with the computing device apparatus;

configuration registers configured to store configuration profile data for currently active settings of the computing components, wherein each computing component contains at least one of the configuration registers;

a system bus;

one or more non-volatile logic arrays configured to store a plurality of configuration profiles for individual settings of the computing components;

a dedicated bus separate from the system bus and connecting the one or more non-volatile logic arrays and the configuration registers, the dedicated bus being coupled in common to the configuration registers;

a non-volatile memory controller configured to control the one or more non-volatile logic arrays, receive a plurality of different triggers, and effecting transfer of different ones of the plurality of configuration profiles to associated ones of the configuration registers based on which of the plurality of different triggers are received by the non-volatile memory controller; and

a non-volatile array output multiplexer arranged to selectively couple individual rows of the one or more non-volatile logic arrays to the dedicated bus so that a configuration profile stored in a selected one of the individual rows can be transferred to an associated one of the configuration registers over the dedicated bus, wherein each of the individual rows of the one or more non-volatile logic arrays is coupled to a respective input of the non-volatile array output multiplexer, and wherein the dedicated bus is coupled to an output of the non-volatile array output multiplexer;

wherein the non-volatile memory controller is configured to transfer at least one of the plurality of configuration profiles to associated ones of the configuration registers using a sub-system clock for a non-volatile logic sub-system for the one or more non-volatile logic arrays, the sub-system clock operating at a higher clock speed than a system clock of the computing device.

10. The computing device apparatus of claim 9, wherein the computing device apparatus is configured to generate individual one of the plurality of different triggers as either or both of a software trigger or a hardware trigger.

11. The computing device apparatus of claim 9, wherein computing device apparatus is configured to be modifiable by a user to customize the plurality of the different triggers and associated transfer of the configuration profiles.

12. The computing device apparatus of claim 9, wherein the one or more non-volatile logic arrays are configured to store device module identifier information or peripheral identifier information for individual ones of the plurality of configuration profiles.

13. The computing device apparatus of claim 9, wherein the non-volatile memory controller is configured to transfer at least one of the plurality of configuration profiles to associated ones of the configuration registers according to a hard-coded state machine.