Controlling aggregate signal amplitude from device arrays by segmentation and time-gating

• US 10,453,528 B1
• Filed: 06/14/2018
• Issued: 10/22/2019
• Est. Priority Date: 06/14/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Burr, Geoffrey W., Narayanan, Pritish
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US16/008,966
• Time in Patent Office: 495 Days
• CPC Class Codes: G06N 3/02 Neural networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

High dynamic range resistive arrays are provided. An array of resistive elements provides a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values and (ii) a matrix of analog resistive weights within the array. First stage current mirrors are electrically coupled to a subset of the resistive elements through a local current accumulation wire. A second stage current mirror is electrically coupled to the first stage current mirrors through a global accumulation wire. Each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale up or down the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.

Claims

1. A circuit, comprising:

an array of resistive elements, the array providing a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values and (ii) a matrix of analog resistive weights within the array;

first stage current mirrors, each of the first stage current mirrors being electrically coupled to a subset of the resistive elements through a local current accumulation wire; and

a second stage current mirror, the second stage current mirror being electrically coupled to the first stage current mirrors through a global accumulation wire, wherein

each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.

2. The circuit of claim 1, further comprising:

a time-gating circuit adapted to periodically enable at least one of the first stage and/or second stage current mirrors, thereby controlling the fraction of time during which current is applied to the global accumulation wire.

3. The circuit of claim 1, the second stage current mirror comprising at least one component having scaling factors selectable to scale the current from the global current accumulation wire.

4. The circuit of claim 1, further comprising:

a plurality of local accumulation wires, each of which is connected to a respective subset of the resistive elements.

5. The circuit of claim 1, wherein the subset of resistive elements corresponds to one or more columns of the array.

6. The circuit of claim 1, wherein the subset of resistive elements corresponds to one or more rows of the array.

7. The circuit of claim 1, wherein the resistive elements are non-volatile memory devices.

8. The circuit of claim 1, wherein the resistive elements are transistors whose gate terminals are connected to respective capacitors.

9. The circuit of claim 1, wherein the resistive elements store synaptic weights of a neural network.

10. A circuit, comprising:

an array of resistive elements, the array providing a current output equal to the strength of a stored analog resistive weight within the array;

first stage current mirrors, each of the first stage current mirrors being electrically coupled to a subset of the resistive elements through a local current accumulation wire; and

a second stage current mirror, the second stage current mirror being electrically coupled to the first stage current mirrors through a global accumulation wire, wherein

each of the first stage current mirrors includes at least one component having respective scaling factors selectable to amplify the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.

11. The circuit of claim 10, further comprising:

a time-gating circuit adapted to periodically enable at least one of the first stage and/or second stage current mirrors, thereby controlling the fraction of time during which current is applied to the global accumulation wire.

12. The circuit of claim 10, the second stage current mirror comprising at least one component having scaling factors selectable to amplify the current from the global current accumulation wire.

13. The circuit of claim 10, further comprising:

a plurality of local accumulation wires, each connected to a subset of the resistive elements.

14. The circuit of claim 10, wherein the subset of resistive elements corresponds to one or more columns of the array.

15. The circuit of claim 10, wherein the subset of resistive elements corresponds to one or more rows of the array.

16. The circuit of claim 10, wherein the resistive elements are non-volatile memory devices.

17. The circuit of claim 10, wherein the resistive elements are transistors whose gate terminals are connected to respective capacitors.

18. The circuit of claim 10, wherein the resistive elements store synaptic weights of a neural network.

19. A method, comprising:

providing a vector of voltage inputs to an array of resistive elements, the array adapted to provide a vector of current outputs equal to the analog dot-product between the vector of voltage inputs and a vector of analog resistive weights within the array, wherein

first stage current mirrors are electrically coupled to a subset of the resistive elements through a local current accumulation wire,

a second stage current mirror is electrically coupled to the first stage current mirrors through a global accumulation wire, and

each of the first stage current mirrors includes components having respective scaling factors; and

;

controlling an aggregate current on the global accumulation wire by selecting a scaling factor for the components of the first stage current mirrors.