Data storage system with configurable prefetch buffers

• US 10,459,842 B1
• Filed: 02/24/2018
• Issued: 10/29/2019
• Est. Priority Date: 12/31/2016
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Bruce, Rey H., Bruce, Ricardo H., Verdan, Marlon B., Tagayo-Villapana, Elsbeth Lauren
• Primary Examiner(s): Peugh, Brian R
• Application Number:
  US15/904,322
• Time in Patent Office: 612 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

Abstract

In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

Claims

1. An apparatus comprising:

a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer;

wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and

wherein any of the prefetch buffers is configured to store prefetch data.

2. The apparatus of claim 1, wherein the prefetch data is available to a host that sends a memory read transaction request to the data storage device.

3. The apparatus of claim 1, wherein the data storage device further comprises a first non-volatile memory controller comprising the first prefetch buffer, a second non-volatile memory controller comprising the second prefetch buffer, and a third non-volatile memory controller comprising the third prefetch buffer.

4. The apparatus of claim 1, wherein the data storage device comprises:

a first non-volatile memory controller, a second non-volatile memory controller, and a third non-volatile memory controller;

a first non-volatile memory device coupled to the first non-volatile memory controller;

a second non-volatile memory device coupled to the second non-volatile memory controller; and

a third non-volatile memory device coupled to the third non-volatile memory controller;

wherein the first prefetch buffer comprises a first data register in the first non-volatile memory device;

wherein the second prefetch buffer comprises a second data register in the second non-volatile memory device;

wherein the third prefetch buffer comprises a third data register in the third non-volatile memory device.

5. The apparatus of claim 1, wherein the second prefetch buffer and the third prefetch buffer are disposed in a same direction.

6. The apparatus of claim 1, wherein the second prefetch buffer is disposed in a first direction and the third prefetch buffer is disposed in a second direction.

7. The apparatus of claim 1, further comprising a fourth prefetch buffer that is coupled to the first prefetch buffer and that is parallel to the second prefetch buffer and the third prefetch buffer.

8. The apparatus of claim 7, wherein the second prefetch buffer is disposed in a first direction, the third prefetch buffer is disposed in a second direction, and the fourth prefetch buffer is disposed in a third direction.

9. The apparatus of claim 8, wherein the first direction is disposed along a first axis, the second direction is disposed along a second axis, and the third direction is disposed along a third axis;

and

wherein the first axis, the second axis, and the third axis are orthogonal with respect to each other so that the first axis, the second axis, and the third axis form a three-dimensional coordinate system.

10. The apparatus of claim 8, wherein at least one of the first direction, second direction, or third direction is at an angular offset from a first axis;

and

wherein the first axis, a second axis, and a third axis are orthogonal with respect to each other so that the first axis, the second axis, and the third axis form a three-dimensional coordinate system.

11. The apparatus of claim 1, further comprising a fourth prefetch buffer that is coupled in series to the first prefetch buffer or to the third prefetch buffer.

12. The apparatus of claim 11, wherein the second prefetch buffer is disposed in a first direction, the third prefetch buffer is disposed in a second direction, and the fourth prefetch buffer is disposed in a third direction.

13. The apparatus of claim 11, wherein the first direction is disposed along a first axis, the second direction is disposed along a second axis, and the third direction is disposed along a third axis;

and

wherein the first axis, the second axis, and the third axis are orthogonal with respect to each other so that the first axis, the second axis, and the third axis form a three-dimensional coordinate system.

14. The apparatus of claim 11, wherein at least one of the first direction, second direction, or third direction is at an angular offset from a first axis;

and

wherein the first axis, a second axis, and a third axis are orthogonal with respect to each other so that the first axis, the second axis, and the third axis form a three-dimensional coordinate system.

15. The apparatus of claim 1, further comprising:

a fourth prefetch buffer and a fifth prefetch buffer, wherein the fourth prefetch buffer and the fifth prefetch buffer are both coupled in parallel to the third prefetch buffer; and

wherein any of the prefetch buffers is configured to store prefetch data.

16. The apparatus of claim 15, wherein the fourth prefetch buffer is disposed in a first direction and the fifth prefetch buffer is disposed in a second direction.

17. The apparatus of claim 16, wherein the first direction is disposed along a first axis and the second direction is disposed along a second axis;

and

wherein the first axis and the second axis are orthogonal with respect to each other.

18. The apparatus of claim 17, wherein at least one of the first direction and second direction is at an angular offset from the first axis.

19. A method, comprising:

storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a data storage device;

wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer.

20. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a data storage device;

wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer.