Semiconductor device, display device, and electronic device

• US 10,460,683 B2
• Filed: 08/23/2017
• Issued: 10/29/2019
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujita, Masashi
• Primary Examiner(s): Rosario, Nelson M
• Application Number:
  US15/684,051
• Publication Number:
  US 20180061335A1
• Time in Patent Office: 797 Days
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 2201/44 Arrangements combining different electro-active layers, e.g. electrochromic, liquid crystal or electroluminescent layers
• CPC Class Codes: G08C 19/36 using optical means to covert the input signal characterised by optical transfer means G01D5/26; optical analogue digital converters G02F7/00
• CPC Class Codes: G09G 2300/046 with an emissive area and a light-modulating area combined in one pixel
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/08 with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a novel semiconductor device or display device. The semiconductor device includes a decoder circuit, an amplifier circuit, and an arithmetic circuit. The amplifier circuit includes a first amplifier and a second amplifier. One of the first amplifier and the second amplifier has a function of inspecting an output of the other of the first amplifier and the second amplifier. The arithmetic circuit has a function of calculating an error of a potential output from the first amplifier or the second amplifier, on the basis of a result of the inspection. The decoder circuit has a function of correcting a video signal input to the decoder circuit by subtracting the error of the potential from the video signal.

Claims

1. A semiconductor device comprising:

a decoder circuit;

an amplifier circuit; and

an arithmetic circuit,

wherein the amplifier circuit comprises a first amplifier and a second amplifier,

wherein one of the first amplifier and the second amplifier is configured to inspect an output of the other of the first amplifier and the second amplifier,

wherein the arithmetic circuit is configured to calculate an error of a potential output from the first amplifier or the second amplifier, on the basis of a result of the inspection, and

wherein the decoder circuit is configured to correct a video signal input to the decoder circuit by subtracting the error of the potential from the video signal.

2. The semiconductor device according to claim 1,

wherein the video signal is digital data, and

wherein the arithmetic circuit is configured to calculate the error of the potential with use of the digital data.

3. A display device comprising:

the semiconductor device according to claim 1; and

a pixel portion,

wherein the pixel portion includes a plurality of pixels, and

wherein the semiconductor device is configured to supply a potential corresponding to a corrected video signal to the pixel.

4. An electronic device comprising:

the display device according to claim 3; and

a processor,

wherein the processor is configured to select whether to make the semiconductor device supply a video signal to the pixel portion or make the semiconductor device perform the inspection.

5. A semiconductor device comprising:

a decoder circuit;

an amplifier circuit; and

an arithmetic circuit,

wherein the amplifier circuit comprises a first amplifier and a second amplifier,

wherein one of the first amplifier and the second amplifier is configured to inspect an output of the other of the first amplifier and the second amplifier,

wherein the arithmetic circuit is configured to calculate an error of a potential output from the first amplifier or the second amplifier, on the basis of a result of the inspection,

wherein the decoder circuit is configured to correct a video signal input to the decoder circuit by subtracting the error of the potential from the video signal,

wherein the first amplifier comprises a first operational amplifier,

wherein the second amplifier comprises a second operational amplifier, a first switch, and a second switch,

wherein a first terminal of the first switch is electrically connected to an inverting input terminal of the second operational amplifier,

wherein a second terminal of the first switch is electrically connected to an output terminal of the second operational amplifier,

wherein a first terminal of the second switch is electrically connected to the inverting input terminal of the second operational amplifier,

wherein a second terminal of the second switch is electrically connected to an output terminal of the first operational amplifier, and

wherein the second operational amplifier is configured to output a signal corresponding to an inspection result of an output of the first operational amplifier to the arithmetic circuit.

6. The semiconductor device according to claim 5,

wherein the output of the first operational amplifier is inspected by turning on the second switch so that a potential supplied to a non-inverting input terminal of the second operational amplifier is gradually changed.

7. The semiconductor device according to claim 5,

wherein the first switch and the second switch are each composed of a transistor, and

wherein the transistor includes a metal oxide in a channel formation region.

8. A display device comprising:

a decoder circuit;

an amplifier circuit;

an arithmetic circuit;

a pixel portion; and

a D/A converter circuit,

wherein the amplifier circuit comprises a first amplifier and a second amplifier,

wherein one of the first amplifier and the second amplifier is configured to inspect an output of the other of the first amplifier and the second amplifier,

wherein the arithmetic circuit is configured to calculate an error of a potential output from the first amplifier or the second amplifier, on the basis of a result of the inspection,

wherein the decoder circuit is configured to correct a video signal input to the decoder circuit by subtracting the error of the potential from the video signal,

wherein the pixel portion includes a plurality of pixels,

wherein the D/A converter circuit comprises a selection circuit and a potential generation circuit,

wherein the potential generation circuit is configured to supply a plurality of reference potentials to the selection circuit, and

wherein a first number of the reference potentials is larger than a second number of grey levels displayed by the pixels.

9. The display device according to claim 8, further comprising:

a first driver circuit comprising the semiconductor device; and

a second driver circuit comprising the semiconductor device,

wherein the pixel portion comprises a first pixel comprising a liquid crystal element and a second pixel comprising a light-emitting element,

wherein the first driver circuit is configured to supply a video signal to the first pixel,

wherein the second driver circuit is configured to supply a video signal to the second pixel,

wherein the potential generation circuit in the first driver circuit is configured to generate the reference potential with use of a first potential,

wherein the potential generation circuit in the second driver circuit is configured to generate the reference potential with use of a second potential,

wherein when the potential generation circuit in the first driver circuit generates the reference potential, the first potential is supplied to the potential generation circuit in the first driver circuit,

wherein when the potential generation circuit in the second driver circuit generates the reference potential, the second potential is supplied to the potential generation circuit in the second driver circuit, and

wherein when the inspection is performed, the first potential is supplied to the potential generation circuit in each of the first driver circuit and the second driver circuit.