Multichannel-based signal transmission method and apparatus

• US 10,461,974 B2
• Filed: 01/14/2019
• Issued: 10/29/2019
• Est. Priority Date: 07/15/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Wu, Tao, Chen, Teyan
• Primary Examiner(s): Murillo Garcia, Fabricio R
• Application Number:
  US16/246,761
• Publication Number:
  US 20190149375A1
• Time in Patent Office: 288 Days
• Field of Search: 375298
• CPC Class Codes: H04L 27/183 Multiresolution systems
• CPC Class Codes: H04L 27/2042 with more than two phase states
• CPC Class Codes: H04L 27/2057 with a separate carrier for each phase state
• CPC Class Codes: H04L 27/2605 Symbol extensions, e.g. Zero Tail, Unique Word [UW]
• CPC Class Codes: H04L 27/3488 Multiresolution systems
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 5/001 the frequencies being arranged in component carriers
• CPC Class Codes: H04L 5/0046 Determination of how many bits are transmitted on different sub-channels

Abstract

This application provides a multichannel-based signal transmission method and apparatus. The method includes: combining N groups of lower-order modulation symbols into N groups of higher-order modulation symbols, where an ith higher-order modulation symbol in each group of higher-order modulation symbols is obtained by combining ith lower-order modulation symbols in all the N groups of lower-order modulation symbols, each group of lower-order modulation symbols includes M lower-order modulation symbols, i=1, 2, . . . , M, N is a positive integer greater than 1, and M is a positive integer greater than 1; determining N to-be-sent signals based on the N groups of higher-order modulation symbols; and sending a kth to-be-sent signal in the N to-be-sent signals by using a kth channel in N channels, where k=1, 2, . . . , N.

Claims

1. A method, comprising:

combining, by a first device, N groups of lower-order modulation symbols into N groups of higher-order modulation symbols, wherein each of the N groups of lower-order modulation symbols comprises M lower-order modulation symbols, N is a positive integer greater than 1, M is a positive integer greater than 1, and wherein combining the N groups of lower-order modulation symbols into the N groups of higher-order modulation symbols comprises;

forming an ith column vector using an ith lower-order modulation symbol from each of the N groups of lower-order modulation symbols, wherein i is an integer from 1 to M; and

for each integer value of s from 1 to N, determining a product of a row vector of an sth row in a matrix Q and the ith column vector as an ith higher-order modulation symbol in an sth group of higher-order modulation symbols in the N groups of higher-order modulation symbols;

determining, by the first device, N to-be-sent signals based on the N groups of higher-order modulation symbols; and

for each integer value of k from 1 to N, sending, by the first device to a second device, a k^th to-be-sent signal in the N to-be-sent signals using a k^th channel in N channels, wherein the first device is a user equipment and the second device is a base station, or the first device is a base station and the second device is a user equipment.

2. The method according to claim 1, wherein determining the N to-be-sent signals based on the N groups of higher-order modulation symbols comprises:

determining N first guard intervals; and

for each integer value of t from 1 to N, inserting a t^th first guard interval in the N first guard intervals at a location following a t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain a t^th to-be-sent signal.

3. The method according to claim 2, wherein determining the N first guard intervals comprises:

determining N groups of first guard signals, wherein each of the N groups of first guard signals comprises G first guard signals, and G is a positive integer greater than 1; and

for each integer value of t from 1 to N, determining a sequence formed by a t^th group of first guard signals in the N groups of first guard signals as the t^th first guard interval in the N first guard intervals.

4. The method according to claim 3, wherein for each integer value of t from 1 to N, inserting the t^th first guard interval in the N first guard intervals at the location following the t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain the t^th to-be-sent signal, comprises, for each integer value of t from 1 to N, performing the following:

performing a phase shift on an i^th higher-order modulation symbol in the t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain a t^th group of phase-shifted higher-order modulation symbols, wherein a phase shift factor of the phase shift is

5. The method according to claim 1, wherein the matrix Q is one of the following matrices:

6. The method according to claim 1, wherein a value of N is 2, each lower-order modulation symbol is a binary phase shift keying (BPSK) symbol, and each higher-order modulation symbol is a quadrature phase shift keying (QPSK) symbol.

7. The method according to claim 1, wherein a bandwidth of each of the N channels is 2.16 GHz or 4.32 GHz.

8. An apparatus, comprising:

a processor, configured to;

combine N groups of lower-order modulation symbols into N groups of higher-order modulation symbols, wherein each of the N groups of lower-order modulation symbols comprises M lower-order modulation symbols, N is a positive integer greater than 1, M is a positive integer greater than 1, and wherein combining the N groups of lower-order modulation symbols into the N groups of higher-order modulation symbols comprises;

forming an ith column vector using an ith lower-order modulation symbol from each of the N groups of lower-order modulation symbols, wherein i is an integer from 1 to M; and

for each integer value of s from 1 to N, determining a product of a row vector of an sth row in a matrix Q and the ith column vector as an ith higher-order modulation symbol in an sth group of higher-order modulation symbols in the N groups of higher-order modulation symbols; and

determine N to-be-sent signals based on the N groups of higher-order modulation symbols; and

a transceiver, configured to send to a second device, for each integer value of k from 1 to N, a k^th to-be-sent signal in the N to-be-sent signals using a k^th channel in N channels, wherein the apparatus is comprised in a first device, and wherein the first device is a user equipment and the second device is a base station, or the first device is a base station and the second device is a user equipment.

9. The apparatus according to claim 8, wherein the processor being configured to determine the N to-be-sent signals based on the N groups of higher-order modulation symbols comprises the processor being configured to:

determine N first guard intervals; and

for each integer value of t from 1 to N, insert a t^th first guard interval in the N first guard intervals at a location following a t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain a t^th to-be-sent signal.

10. The apparatus according to claim 9, wherein the processor being configured to determine the N first guard intervals comprises the processor being configured to:

determine N groups of first guard signals, wherein each of the N groups of first guard signals comprises G first guard signals, and G is a positive integer greater than 1; and

for each integer value oft from 1 to N, determine a sequence formed by a t^th group of first guard signals in the N groups of first guard signals as the t^th first guard interval in the N first guard intervals.

11. The apparatus according to claim 10, wherein the processor being configured to, for each integer value oft from 1 to N, insert the t^th first guard interval in the N first guard intervals at the location following the t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain the t^th to-be-sent signal, comprises the processor is being configured to:

perform a phase shift on an i^th higher-order modulation symbol in the t^th group of higher-order modulation symbols in the N groups of higher-order modulation symbols, to obtain a t^th group of phase-shifted higher-order modulation symbols, wherein a phase shift factor of the phase shift is

12. The apparatus according to claim 8, wherein the matrix Q is one of the following matrices:

13. The apparatus according to claim 8, wherein a value of N is 2, each lower-order modulation symbol is a binary phase shift keying (BPSK) symbol, and each higher-order modulation symbol is a quadrature phase shift keying (QPSK) symbol.

14. The apparatus according to claim 8, wherein a bandwidth of each of the N channels is 2.16 GHz or 4.32 GHz.