Checkpointing using FPGA

• US 10,467,116 B2
• Filed: 06/08/2012
• Issued: 11/05/2019
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Lim, Kevin T., AuYoung, Alvin
• Primary Examiner(s): Bonzo, Bryce P
• Assistant Examiner(s): Gibson, Jonathan D
• Application Number:
  US14/396,324
• Publication Number:
  US 20150089285A1
• Time in Patent Office: 2,706 Days
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1446 Point-in-time backing up or restoration of persistent data
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 2201/825 the problem or solution involving locking

Abstract

Methods, systems, and computer-readable and executable instructions are provided for checkpointing using a field programmable gate array (FPGA). Checkpointing using FPGA can include checkpointing data within a region of a server'"'"'s contents to memory and monitoring the checkpointed data using the FPGA.

Claims

1. A computer-implemented method for checkpointing using a field programmable gate array (FPGA) comprising:

temporarily locking a first region of data of a server to prevent access to the data in the first region while allowing access to data in other regions of the server;

checkpointing the data in the first region of the server to memory while the first region is locked;

subsequent to checkpointing the data in the first region, releasing the locking of the first region; and

monitoring the checkpointed data of the first region using the FPGA, wherein the FPGA is coherently coupled to the memory such that the monitoring is performed automatically with the FPGA capturing accesses within the first region and the FPGA invalidates cache lines associated with the data in the first region of the server when it is checkpointing.

2. The method of claim 1, wherein accesses to the memory are broadcast to the FPGA.

3. The method of claim 1, wherein checkpointing the data to the memory further comprises checkpointing the data to non-volatile memory.

4. The method of claim 1, further comprising utilizing the checkpointed data to recover the server in response to the server crashing.

5. The method of claim 1, further comprising compressing the data in the first region before checkpointing the data to the memory.

6. The method of claim 1, wherein monitoring the data further comprises excluding expired data entries from the first region.

7. A non-transitory computer-readable medium storing a set of instructions executable by a processing resource to:

temporarily lock a first region of data in a memcached server using a field-programmable gate array (FPGA) to prevent access to the data in the first region while allowing access to other regions of data in the memcached server;

checkpoint the first region of data of the memcached server to non-volatile memory while the first region of the memcached server is locked;

release the lock for a period of time;

lock a second region of data of the memcached server;

checkpoint the second region of data of the memcached server to the non-volatile memory while the second region of the memcached server is locked; and

monitor the checkpointed data within the first and second regions using the FPGA, wherein the FPGA is coherently attached to the non-volatile memory such that the monitoring is performed automatically with the FPGA capturing accesses within the first and second regions and the FPGA invalidates cache lines associated with the first and second regions of data when they are checkpointing.

8. The non-transitory computer-readable medium of claim 7, wherein the instructions are further executable to monitor the data by tracking an update to each of the first and second regions.

9. The non-transitory computer-readable medium of claim 7, wherein the memcached server includes a memcached hash table, and wherein the instructions are further executable to divide the memcached hash table into regions for locking and releasing the lock.

10. The non-transitory computer-readable medium of claim 7, wherein the instructions are further executable to temporarily reduce region updates during checkpointing.

11. The non-transitory computer-readable medium of claim 7, wherein the instructions are further executable to receive, at the FPGA, information about a hash table of the first and second regions and data within each of the first and second regions.

12. A system for checkpointing using a field-programmable gate array (FPGA), comprising:

a memory resource; and

a processing resource coupled to the memory resource, to;

receive a number of address regions within a memcached server to checkpoint;

temporarily lock a first address region to prevent access data in the first address region while allowing access data in other address regions of the memcached server;

checkpoint the first address region to non-volatile memory while the first address region is locked; and

monitor the data in the first address region using the FPGA, wherein the FPGA is coherently coupled to the non-volatile memory such that the monitoring is performed automatically with the FPGA capturing accesses within the first address region and the FPGA invalidates cache lines associated with the first address region when it is checkpointing.

13. The system of claim 12, wherein the processing resource is further coupled to the memory resource to allow the FPGA access to a memcached hash table lock within one of the number of address regions.

14. The system of claim 12, wherein the processing resource is further coupled to the memory resource to save to the non-volatile memory at least one of a pointer to a start of one of the number of address regions, a size of an address region checkpoint, and an address for a beginning of a memcached hash table.

15. The system of claim 12, wherein the FPGA is located in a separate network socket from the non-volatile memory.