Display device with light blocking layer and manufacturing method thereof

• US 10,475,872 B2
• Filed: 10/20/2016
• Issued: 11/12/2019
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Yang, Heejung, Kim, Hyungtae, Jang, Dongun, Kim, Dongsun, Ho, Wonjoon
• Primary Examiner(s): Gordon, Matthew E.
• Application Number:
  US15/298,749
• Publication Number:
  US 20170117344A1
• Time in Patent Office: 1,118 Days
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 2102/341 Short-circuit prevention
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/351 comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Abstract

Provided are a display device and a method of manufacturing the same. A display device includes: a light blocking layer on a first substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer, an insulating layer on the semiconductor layer, and a source/drain metal layer positioned on the insulating layer, the source/drain metal layer including a non-overlap region that does not overlap the light blocking layer.

Claims

1. A display device, comprising:

a light blocking layer on a first substrate;

a buffer layer on the light blocking layer;

a semiconductor layer on the buffer layer;

a dummy metal layer on and directly contacting the semiconductor layer, the dummy metal layer including an opening exposing an entirety of a channel region of the semiconductor layer;

an insulating layer on the semiconductor layer in the opening and not directly contacting the dummy metal layer;

a source/drain metal layer on the insulating layer, the source/drain metal layer comprising a non-overlap region that does not overlap the light blocking layer, and overlaps the semiconductor layer; and

a gate metal layer on the insulating layer,

wherein no portion of the dummy metal layer overlaps the gate metal layer in any part of the channel region of the semiconductor layer.

2. The display device of claim 1, wherein the non-overlap region has a size greater than or equal to a size of a region in which the semiconductor layer and the source/drain metal layer are electrically connected.

3. The display device of claim 1, wherein the non-overlap region:

is at an outer edge of one surface of an upper end of the light blocking layer; and

has a quadrangular shape.

4. The display device of claim 1, wherein the non-overlap region:

is on an outer edge of a side surface of an upper end of the light blocking layer; and

has a quadrangular shape.

5. The display device of claim 1, wherein the non-overlap region is in a region adjacent to an insulated gate metal layer on the semiconductor layer.

6. The display device of claim 1, wherein at least one of the light blocking layer, the gate metal layer, and the source/drain metal layer comprises multiple layers comprising a light-absorbing layer.

7. The display device of claim 3, wherein the light blocking layer faces the non-overlap region on three sides in plan view.

8. The display device of claim 4, wherein the light blocking layer faces the non-overlap region on three sides in plan view.

9. The display device of claim 1, wherein the dummy metal layer has a shape corresponding to the semiconductor layer, except for the region corresponding to the channel region of the semiconductor layer.

10. The display device of claim 1, further comprising:

a contact hole in the insulating layer,

wherein a position of the contact hole corresponds to the non-overlap region.

11. The display device of claim 10, wherein the non-overlap region occupies a region larger than the contact hole.

12. The display device of claim 1, wherein the source/drain metal layer directly contacts the dummy metal layer.