Positive logic digitally tunable capacitor

• US 10,476,484 B2
• Filed: 01/15/2018
• Issued: 11/12/2019
• Est. Priority Date: 09/02/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio
• Primary Examiner(s): Chen, Patrick C
• Application Number:
  US15/871,643
• Publication Number:
  US 20180159511A1
• Time in Patent Office: 666 Days
• Field of Search: 327109
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03J 3/16 Tuning without displacement of reactive element, e.g. by varying permeability
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03J 5/24 with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Claims

1. An integrated circuit block comprising:

a first node;

a second node;

a resistive network;

a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and

supply rails providing a first supply voltage and a second supply voltage;

wherein;

a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;

the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;

each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;

the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches;

the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting a capacitance between the first node and the second node;

the second supply voltage is a mid-rail voltage;

the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of FET switches; and

the resistive network comprises a plurality of resistors;

the plurality of resistors being coupled across drain and source terminals of corresponding FET switches, and a series resistor, the series resistor coupling a resistor of the plurality of resistors to the second supply voltage.

2. The integrated circuit block of claim 1, wherein the first supply voltage and the second supply voltage are inverted versions of each other.

3. The integrated circuit block of claim 1, wherein a gate voltage on a FET switch connected to the first supply voltage is either higher or lower than a drain voltage on a corresponding FET switch drain connected to the second supply voltage.

4. The integrated circuit block of claim 1, wherein the plurality of FET switches are four terminal FETs, a body of the four terminal FETs being connected to a supply voltage through a plurality of resistors.

5. The integrated circuit block of claim 1, wherein the two or more capacitors have same capacitances.

6. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 5, wherein the plurality of integrated circuit blocks are configured in parallel.

7. The integrated circuit block of claim 1, wherein the first supply voltage and the second supply voltage are configured such that a voltage across gate-source terminals of the FET switches is smaller or equal to a maximum allowable voltage level.

8. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 1, wherein the plurality of integrated circuit blocks are configured in parallel.

9. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 1, wherein the plurality of integrated circuit blocks are configured in parallel.

10. The integrated circuit block of claim 1, wherein the plurality of resistors have same resistances.

11. The integrated circuit block of claim 1, wherein the plurality of FET switches comprises two or more FET switches configured to withstand a voltage greater than a voltage withstood by one switch.

12. The integrated circuit block of claim 1, wherein the non-negative supply voltages are positive supply voltages regardless of states of the plurality of FET switches.

13. A method of digitally tuning a capacitor in an integrated circuit, the method comprising the steps of:

providing a first node;

providing a second node;

providing a series arrangement of two or more capacitors and a plurality of FET switches;

the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;

providing a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches, the second supply voltage being a mid-rail voltage;

providing a resistive network, the resistive network comprising;

a plurality of resistors coupled across drain and source terminals of corresponding FET switches, and

a series resistor, connecting a resistor of the plurality of resistors to the second supply voltage;

providing a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;

coupling the series arrangement of two or more capacitors and the plurality of FET switches between the first node and the second node;

coupling a first capacitor of the two or more capacitors to the first node and coupling a second capacitor of the two or more capacitors to the second node; and

enabling or disabling the FET switches using the first supply voltage and the second supply voltage and thereby adjusting a capacitance between the first node and the second node.

14. The method of claim 13, wherein the first supply voltage and the second supply voltage are inverted versions of each other.

15. An integrated circuit block comprising:

a first node;

a second node;

a resistive network;

a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and

supply rails providing a first supply voltage and a second supply voltage;

wherein;

a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;

the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;

each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;

the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches;

the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting a capacitance between the first node and the second node;

the second supply voltage is a mid-rail voltage;

the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of FET switches; and

the integrated circuit block is devoid of;

any capacitor coupled across a drain or a source of any FET switch of the plurality of FET switches; and

any capacitor coupled across a drain or a source of any FET switch of the plurality of FET switches and a drain or a source of any other FET switch of the plurality of FET switches.

16. An integrated circuit block comprising:

a first node;

a second node;

a resistive network;

a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and

supply rails providing a first supply voltage and a second supply voltage;

wherein;

a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;

the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;

each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;

the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches;

the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting a capacitance between the first node and the second node;

the second supply voltage is a mid-rail voltage;

the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of FET switches; and

the resistive network comprises a plurality of resistors, the plurality of resistors having first terminals connected to drains of corresponding FET switches and second terminals connected to the second supply voltage;

the resistive network further comprising an end resistor, the end resistor connecting a source of the second end FET switch to the second supply voltage.

17. The integrated circuit block of claim 16, wherein the plurality of resistors has same resistances.

18. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 16, wherein the plurality of integrated circuit blocks are configured in parallel.