Gate driver and configuration system and configuration method thereof

• US 10,482,836 B2
• Filed: 09/27/2016
• Issued: 11/19/2019
• Est. Priority Date: 10/16/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Gao, Xianyong, Hsu, Yihjen, Xiao, Lijun, Hou, Shuai, Xu, Bo, Liang, Lisheng, Fu, Siqing, Shang, Fei, Qiu, Haijun
• Primary Examiner(s): Jansen, II, Michael J
• Application Number:
  US15/515,610
• Publication Number:
  US 20170301305A1
• Time in Patent Office: 1,148 Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A gate driver, a configuration system, and configuration method thereof is provided. The gate driver is used for providing a gate drive signal for a TFT array substrate and comprises at least a drive capability detection module and a drive capability adjustment module. The configuration system is configured to configure the driving capabilities of a plurality of gate drivers and comprises a controller provided outside the plurality of gate drivers. The driving capability of the gate driver becomes adjustable and configurable. The well balance of the drive capabilities of the drive control signals received by the different TFT array regions driven by the plurality of gate drivers configured by the configuration system can avoid the occurrence of a splitting-screen phenomenon.

Claims

1. A gate driver for providing a gate drive signal for a thin film transistor array substrate, the gate driver comprising:

a driving capability detector configured to receive at least the gate drive signal and to detect a driving capability of the gate drive signal based at least on the gate drive signal, the driving capability being represented by a rising time taken by the gate drive signal in form of a voltage pulse signal to rise from a low level to a high level, wherein the driving capability detector is further configured to output a detection signal indicative of the driving capability to an external controller;

a register configured to receive and store an adjustment instruction in form of a digital signal from the external controller;

a push-pull output circuit comprising a first MOS transistor and a second MOS transistor connected in series; and

a driving capability adjustor connected in series with the first and second MOS transistors and between the first and second MOS transistors, wherein the driving capability adjustor is configured to adjust the driving capability of the gate drive signal in response to the adjustment instruction stored in the register.

2. The gate driver according to claim 1, wherein the driving capability detector comprises:

a comparator comprising a first input end to receive a reference voltage and a second input end to receive the gate drive signal, wherein the comparator is configured to compare the gate drive signal with the reference voltage to determine whether the gate drive signal has risen from a low level to the reference voltage; and

a counter configured to determine a time period taken by the gate drive signal to rise from the low level to the reference voltage and to output a count value indicative of the time period.

3. The gate driver according to claim 2, wherein the counter is configured to determine the time period using a standard clock signal and to output the count value as the detection signal.

4. The gate driver according to claim 2, wherein the driving capability detector comprises a voltage divider comprising a first resistor and a second resistor connected in series, wherein the voltage divider is configured to provide the reference voltage, and wherein the first input end of the comparator is electrically connected to a node connected between the first resistor and the second resistor to receive the reference voltage.

5. The gate driver according to claim 1, wherein the driving capability adjustor is selected from a group consisting of a digital potentiometer, a digital capacitor, and a circuit formed by a digital potentiometer or a digital capacitor.

6. The gate driver according to claim 1, wherein the first MOS transistor is connected to a signal source having a high level, and the second MOS transistor is connected to a signal source having a low level;

and

wherein the push-pull output circuit is configured to output the gate drive signal at a node connected between the second MOS transistor and the driving capability adjustor.

7. The gate driver according to claim 1, wherein the detection signal is a digital signal.

8. A configuration system for configuring driving capabilities of a plurality of gate drivers, the plurality gate drivers being used for driving different thin film transistor array regions of a thin film transistor array substrate, the configuration system comprising:

a controller; and

the plurality of gate drivers, wherein each gate driver comprises;

a driving capability detector configured to receive at least a gate drive signal and to detect a driving capability of the gate drive signal based at least on the gate drive signal, the driving capability being represented by a rising time taken by the gate drive signal in form of a voltage pulse signal to rise from a low level to a high level, wherein the driving capability detector is further configured to output a detection signal indicative of the driving capability to the controller;

a register configured to receive and store an adjustment instruction in form of a digital signal from the controller;

a push-pull output circuit comprising a first MOS transistor and a second MOS transistor connected in series; and

a driving capability adjustor connected in series with the first and second MOS transistors and between the first and second MOS transistors, wherein the driving capability adjustor is configured to adjust the driving capability of the gate drive signal in response to the adjustment instruction stored in the register,

wherein the controller is configured to store a plurality of the detection signals output from respective ones of the plurality of gate drivers and to compare the detection signals to generate and output respective adjustment instructions to the respective ones of the plurality of gate drivers.

9. The configuration system according to claim 8, wherein the plurality of gate drivers are provided on a same thin film transistor array substrate.

10. The configuration system according to claim 8, wherein the controller is configured with a driving capability configuration rule and is configured to output the adjustment instructions based on a comparison result between the configuration rule and the detection signals.

11. The configuration system according to claim 10, wherein the driving capability configuration rule is set according to at least one of a) driving capability differences between the gate drive signals output by the plurality of gate drivers, or b) external wiring conditions corresponding to the plurality of gate drivers.

12. The configuration system according to claim 8, wherein each of the plurality of gate drivers comprises an external pin to output the detection signal.

13. A method of using the configuration system of claim 8, the method comprising:

receiving, by the driving capability detectors of the plurality of gate drivers, respective gate drive signals output from the plurality of gate drivers;

detecting, by the driving capability detectors of the plurality of gate drivers, driving capabilities of respective ones of the gate drive signals;

outputting, by the driving capability detectors of the plurality of gate drivers, respective detection signals that reflect the driving capabilities of the gate driving signals; and

comparing, by the controller, the respective detection signals to output respective adjustment instructions to the gate drivers; and

adjusting, by the driving capability adjustors of the plurality of gate drivers, the driving capabilities of the gate drive signals in accordance with the adjustment instructions.

14. The method according to claim 13, wherein the plurality of gate drivers are provide on a same thin film transistor array substrate, the method further comprising driving the same thin film array substrate with the adjusted gate drive signals output from the plurality of gate drivers.

15. The method according to claim 13, further comprising generating, by the controller, the respective adjustment instructions based on a comparison result between a pre-set driving capability configuration rule and the detection signals.

16. The method according to claim 15, wherein the driving capability configuration rule is set according to at least one of driving capability differences between the gate drive signals output by the plurality of gate drivers, or external wiring conditions corresponding to the plurality of gate drivers.