Tap gating scan register, comparator with expected data flip flop

• US 10,488,462 B2
• Filed: 10/03/2018
• Issued: 11/26/2019
• Est. Priority Date: 04/02/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Britt, Cynthia
• Application Number:
  US16/150,744
• Publication Number:
  US 20190033369A1
• Time in Patent Office: 419 Days
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Claims

1. A device comprising:

(a) a scan data input;

(b) a test clock input;

(c) a test mode select input;

(d) test access port circuitry having an input coupled to the test clock input, an input coupled to the test mode select input, a scan clock output, and a control output;

(e) a scan register having an input coupled to the scan data input, an input coupled to the scan clock output, a gated scan enable input, and a scan output;

(f) an inverter having an input coupled to the test clock input and an inverted test clock output;

(g) an expected data flip flop having an input coupled to the scan data input. an input coupled to the inverted test clock output, and an expected data output;

(h) a second flip flop having an input coupled to the test mode select input, an input coupled to the inverted test clock output, and a data output;

(i) gate circuitry having an input coupled to the data output of the second flip flop, an input coupled to the control output, and a gated scan enable output coupled to the gated scan enable input; and

(j) compare circuitry having a first input coupled to the scan output of the scan register and a second input coupled to the expected data output.

2. The device of claim 1 including combinational logic having parallel stimulus inputs and parallel response outputs and in which the scan register includes parallel stimulus outputs coupled to the parallel stimulus inputs and parallel response inputs coupled to the parallel response outputs.

3. The device of claim 1 in which the compare circuitry includes an input coupled to the scan clock output and an input coupled to the gated scan enable output.

4. The device of claim 1 in which the compare circuitry includes a serial test data input and a serial test data output separate from the scan data input and the first input.

5. The device of claim 1 in which the test access port circuitry includes a state machine operating in a Test Logic Reset state, a Run Test/Idle state, Capture states, Shift states, Exit1 states, Pause states, Exit2 states, and Update states.

6. The device of claim 1 in which the gate circuitry is an AND gate.

7. An integrated circuit scan test architecture comprising:

(a) combinational logic having parallel stimulus inputs and parallel response outputs;

(b) a scan data input, a test clock input, and a test mode select input;

(c) test access port circuitry having a state machine operating in states, an input coupled to the test clock input, an input coupled to the test mode select input, a scan clock output, and a control output;

(d) a scan register having an input coupled to the scan data input, an input coupled to the scan clock output, parallel stimulus outputs coupled to the parallel stimulus inputs, parallel response inputs coupled to the parallel response outputs, a gated scan enable input, and a scan output;

(e) an inverter having an input coupled to the test clock input and an inverted test clock output;

(f) an expected data flip flop having an input coupled to the scan data input. an input coupled to the inverted test clock output, and an expected data output;

(g) a second flip flop having an input coupled to the test mode select input, an input coupled to the inverted test clock output, and a data output;

(h) gate circuitry having an input coupled to the data output of the flip flop, an input coupled to the control output, and a gated scan enable output coupled to the gated scan enable input; and

(i) compare circuitry having a first input coupled to the scan output of the scan register and an input coupled to the expected data output.

8. The architecture of claim 7 in which the compare circuitry includes an input coupled to the scan clock output and an input coupled to the gated scan enable output.

9. The architecture of claim 7 in which the compare circuitry includes a serial test data input and a serial test data output separate from the scan data input and the first input.

10. The architecture of claim 7 in which the state machine operates in the states of a Test Logic Reset state, a Run Test/Idle state, Capture states, Shift states, Exit1 states, Pause states, Exit2 states, and Update states.

11. The architecture of claim 7 in which the gate circuitry is an AND gate.