Pixel structure and method of manufacturing the same, array substrate and display device

• US 10,488,697 B2
• Filed: 09/19/2017
• Issued: 11/26/2019
• Est. Priority Date: 01/22/2017
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Wang, Zhidong
• Primary Examiner(s): Nguyen, Sang V
• Application Number:
  US15/708,641
• Publication Number:
  US 20180210274A1
• Time in Patent Office: 798 Days
• CPC Class Codes: G02B 5/1809 with pitch less than or comparable to the wavelength
• CPC Class Codes: G02B 5/1857 using exposure or etching means, e.g. holography, photolithography, exposure to electron or ion beams
• CPC Class Codes: G02B 5/201 in the form of arrays
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/133504 Diffusing, scattering, diffracting elements associated to illuminating devices G02F1/133606
• CPC Class Codes: G02F 1/133521 Interference filters
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/305 diffraction grating
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

Embodiments of the present disclosure provide a pixel structure, including a plurality of sub-pixels arranged in an array, each sub-pixel including a display region and a non-display region, the non-display region of each sub-pixel being formed with a thin film transistor therein, the display region of each sub-pixel being formed therein with a sub-wavelength grating for transmitting therethrough light in a predetermined wavelength range. Embodiments of the present disclosure further provide a method of manufacturing a pixel structure, an array substrate including the pixel structure and a display device.

Claims

1. A pixel structure, comprising a plurality of sub-pixels arranged in an array on a substrate, each sub-pixel comprising a display region and a non-display region, the non-display region of each sub-pixel being formed with a thin film transistor therein, wherein

the display region of each sub-pixel is formed therein with a sub-wavelength grating for transmitting therethrough light in a predetermined wavelength range,

the thin film transistor comprises a gate electrode, and

an orthographic projection of the sub-wavelength grating on the substrate is adjacent to and is not overlapped with an orthographic projection of the gate electrode on the substrate,

wherein the pixel structure comprises at least three sub-pixels, and the sub-wavelength gratings formed in the display regions of respective sub-pixels have different periods or pitches from each other, so as to transmit therethrough light in different predetermined wavelength ranges respectively,

wherein the pixel structure comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, and wherein:

the sub-wavelength grating of the first sub-pixel has a period of 400 nm and a pitch of 121 nm, for transmitting red light therethrough;

the sub-wavelength grating of the second sub-pixel has a period of 350 nm and a pitch of 119 nm, for transmitting green light therethrough; and

the sub-wavelength grating of the third sub-pixel has a period of 440 nm and a pitch of 263 nm, for transmitting blue light therethrough.

2. The pixel structure according to claim 1, wherein each sub-pixel comprises a low temperature polysilicon layer, source and drain electrodes, a gate insulation layer, the gate electrode, an interlayer dielectric layer, a first passivation layer and a planarization layer successively formed on the substrate.

3. The pixel structure according to claim 2, wherein the sub-wavelength grating is only formed in the low temperature polysilicon layer.

4. The pixel structure according to claim 2, wherein the sub-wavelength grating is formed in layers comprising the low temperature polysilicon layer and at least one selected from a group consisting of the gate insulation layer, the interlayer dielectric layer and the first passivation layer.

5. The pixel structure according to claim 1, wherein each sub-pixel comprises the gate electrode, a gate insulation layer, an active layer, source and drain electrodes, and a passivation layer successively formed on the substrate.

6. The pixel structure according to claim 5, wherein the sub-wavelength grating is formed in the active layer.

7. The pixel structure according to claim 5, wherein the sub-wavelength grating is formed in the gate insulation layer.

8. An array substrate, comprising the pixel structure of claim 1.

9. A display device, comprising the array substrate of claim 8, a backlight unit and a liquid crystal unit.

10. A method of manufacturing a pixel structure, comprising:

forming a plurality of sub-pixels arranged in an array on a substrate, each sub-pixel comprising a display region and a non-display region;

forming a thin film transistor in the non-display region of each sub-pixel, the thin film transistor comprising a gate electrode; and

forming a sub-wavelength grating in the display region of each sub-pixel, for transmitting therethrough light in a predetermined wavelength range,

wherein an orthographic projection of the sub-wavelength grating on the substrate is adjacent to and is not overlapped with an orthographic projection of the gate electrode on the substrate,

wherein the step of forming the plurality of sub-pixels arranged in the array on the substrate comprises;

forming at least three sub-pixels arranged in the array on the substrate,

wherein the step of forming the sub-wavelength grating in the display region of each sub-pixel comprises;

forming the sub-wavelength grating in the display region of each of the at least three sub-pixels,

wherein the sub-wavelength grating formed in the display regions of respective sub-pixels have different periods or pitches from each other so as to transmit therethrough light in different predetermined wavelength ranges respectively,

wherein the at least three sub-pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, and wherein;

the sub-wavelength grating of the first sub-pixel has a period of 400 nm and a pitch of 121 nm, for transmitting red light therethrough;

the sub-wavelength grating of the second sub-pixel has a period of 350 nm and a pitch of 119 nm, for transmitting green light therethrough; and

the sub-wavelength grating of the third sub-pixel has a period of 440 nm and a pitch of 263 nm, for transmitting blue light therethrough.

11. The method according to claim 10, further comprising:

forming a low temperature polysilicon layer, source and drain electrodes, a gate insulation layer, the gate electrode, an interlayer dielectric layer, a first passivation layer and a planarization layer successively on the substrate.

12. The method according to claim 11, wherein the step of forming the sub-wavelength grating in the display region of each sub-pixel comprises:

forming the sub-wavelength grating in the low temperature polysilicon layer in the display region of each sub-pixel;

depositing a sacrificial layer on the low temperature polysilicon layer formed therein with the sub-wavelength grating;

removing portions of the sacrificial layer located outside of gaps of the grating;

depositing a gate insulation layer over the low temperature polysilicon layer with the sacrificial layer thereon; and

removing portions of the sacrificial layer located within the gaps of the grating through an etching process.

13. The method according to claim 11, wherein the step of forming the sub-wavelength grating in the display region of each sub-pixel comprises:

forming a sub-wavelength grating in the low temperature polysilicon layer, the gate insulation layer, the interlayer dielectric layer and the first passivation layer within the display region of each sub-pixel;

depositing a sacrificial layer on the first passivation layer formed therein with the sub-wavelength grating;

removing portions of the sacrificial layer located outside of gaps of the grating;

depositing a planarization layer over the first passivation layer with the sacrificial layer thereon; and

removing portions of the sacrificial layer located within the gaps of the grating through an etching process.

14. The method according to claim 10, further comprising:

forming the gate electrode, a gate insulation layer, an active layer, source and drain electrodes, and a passivation layer successively on the substrate.

15. The method according to claim 14, wherein the step of forming the sub-wavelength grating in the display region of each sub-pixel comprises:

forming the sub-wavelength grating in the active layer within the display region of each sub-pixel;

depositing a sacrificial layer on the active layer formed therein with the sub-wavelength grating;

removing portions of the sacrificial layer located outside of gaps of the grating;

depositing a passivation layer over the active layer with portions of the sacrificial layer thereon; and

removing portions of the sacrificial layer located within the gaps of the grating through an etching process.