Memory module with data buffering

• US 10,489,314 B2
• Filed: 12/28/2017
• Issued: 11/26/2019
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Solomon, Jefferey C., Bhakta, Jayesh R.
• Primary Examiner(s): Bansal, Gurtej
• Application Number:
  US15/857,519
• Publication Number:
  US 20180300267A1
• Time in Patent Office: 698 Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

Claims

1. A memory module operable in a computer system to communicate data with a memory controller of the computer system at a specified data rate via a N-bit wide data bus in response to memory commands received from the memory controller, the memory commands including a first memory command and a subsequent second memory command, the first memory command to cause the memory module to receive or output a first burst of N-bit wide data signals and a first burst of data strobes and the second memory command to cause the memory module to receive or output a second burst of N-bit wide data signals and a second burst of data strobes, the memory module comprising:

a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system;

a plurality of memory integrated circuits mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks, wherein the plurality of N-bit wide ranks include a first rank configured to receive or output the first burst of N-bit wide data signals and the first burst of data strobes at the specified data rate in response to the first memory command, and a second rank configured to receive or output the second burst of N-bit wide data signals and the second burst of data strobes at the specified data rate in response to the second memory command;

circuitry coupled between the plurality of N-bit wide ranks and the N-bit wide data bus; and

logic coupled to the circuitry and configured to respond to the first memory command by providing first control signals to the circuitry and to subsequently respond to the second memory command by providing second control signals to the circuitry, wherein the circuitry is configured to enable data transfers through the circuitry in response to the first control signals and subsequently in response to the second control signals, wherein respective N-bit wide data signals of the first burst of N-bit wide data signals and respective data strobes of the first burst of data strobes are transferred at the specified data rate between the first rank and the N-bit wide data bus through the circuitry, and wherein respective N-bit wide data signals of the second burst of N-bit wide data signals and respective data strobes of the second burst of data strobes are transferred at the specified data rate between the second rank and the N-bit wide data bus through the circuitry;

wherein the data transfers through the circuitry are registered data transfers enabled in accordance with an overall CAS latency of the memory module, and the circuitry is configured to add a predetermined amount of time delay for each registered data transfer through the circuitry so that the overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the plurality of memory integrated circuits.

2. The memory module of claim 1, wherein each of the plurality memory integrated circuits has a corresponding load, and wherein the circuitry is configured to isolate the loads of the plurality of memory integrated circuits from the memory controller.

3. The memory module of claim 1, wherein the logic is coupled to the printed circuit board and is further configured to receive from the memory controller a first set of input address and control signals associated with the first memory command and to respond to the first memory command by outputting a first set of registered address and control signals, and wherein the logic is further configured to subsequently receive from the memory controller a second set of input address and control signals associated with the second memory command and to respond to the second memory command by outputting a second set of registered address and control signals, the first set of input address and control signals including a first set of input chip select signals corresponding to respective ranks of the plurality of ranks and the second set of input address and control signals including a second set of input chip select signals corresponding to respective ranks of the plurality of ranks, the first set of registered address and control signals including a first plurality of registered chip select signals corresponding to respective ones of the first plurality of input chip select signals, the second set of registered address and control signals including a second plurality of registered chip select signals corresponding to respective ones of the second plurality of input chip select signals, the first set of registered chip select signals including a first registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value, the second set of registered chip select signals including a second registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value, and wherein the logic is configured to output the first registered chip select signal to the first rank and to output the second registered chip select signal to the second rank.

4. The memory module of claim 1, further comprising an SPD device that reports the overall CAS latency of the memory module to the memory controller.

5. The memory module of claim 1, wherein the memory module is configured to receive from the memory controller an on-die-termination (ODT) signal, wherein each of the plurality of memory integrated circuits includes an ODT circuit, the memory module further comprising a termination circuit external to any of the plurality of memory integrated circuits, wherein the termination circuit is configured to receive the ODT signal and is coupled to the ODT circuit of at least one of the plurality of memory integrated circuits, wherein the termination circuit is configured to provide external termination for the at least one of the plurality of memory integrated circuits in response to the ODT signal, and wherein the ODT circuit of the at least one of the plurality of memory integrated circuits is disabled.

6. The memory module of claim 1, wherein the circuitry includes logic pipelines configured to enable the data transfers through the circuitry in response to the first control signals and subsequently in response to the second control signals.

7. The memory module of claim 1, wherein the logic is further configured to determine the overall CAS latency of the memory module.

8. The memory module of claim 1, wherein N is 64 or 72.

9. The memory module of claim 1, wherein each rank of the plurality of ranks is 72-bits wide, wherein each rank of the plurality of N-bit wide ranks includes 18 4-bit wide memory integrated circuits configured in 9 pairs, wherein a first pair of memory integrated circuits in the first rank is configured to communicate a respective byte of the first burst of N-bit wide data signals in each time interval of a first plurality of time intervals, and wherein a second pair of memory integrated circuits in the second rank is configured to communicate a respective byte of the second burst of N-bit wide data signals in each time interval of a second plurality of time intervals.

10. The memory module of claim 9, wherein the first pair of memory integrated circuits are configured to simulate an 8-bit wide memory device, and the second pair of memory integrated circuits are configured to simulate another 8-bit wide memory device.

11. The memory module of claim 9, further comprising an SPD device programmed with data to characterize each pair of memory integrated circuits as a virtual 8-bit wide memory device.

12. The memory module of claim 1, wherein the respective N-bit wide data signals of the first burst of N-bit wide data signals and the respective data strobes of the first burst of data strobes are transferred through the circuitry during respective time intervals of a first plurality of time intervals, and wherein the respective N-bit wide data signals of the second burst of N-bit wide data signals and the respective data strobes of the second burst of data strobes are transferred through the circuitry during respective time intervals of a second plurality of time intervals.

13. The memory module of claim 1, further comprising a phase locked loop clock driver configured to output a clock signal in response to one or more signals received from the memory controller, wherein the predetermined amount of time delay is at least one clock cycle time delay.

14. The memory module of claim 13, wherein the memory integrated circuits are dynamic random access memory integrated circuits configured to operate synchronously with the clock signal, wherein each memory integrated circuit in the first rank is configured receive or output a respective set of bits of the first burst of N-bit wide data signals on both edges of each of a respective set of data strobes of the first burst of data strobes, and wherein each memory integrated circuit in the second rank is configured receive or output a respective set of bits of the second burst of N-bit wide data signals on both edges of each of a respective set of data strobes of the second burst of data strobes.

15. A memory module operable in a computer system to communicate data with a memory controller of the computer system via a N-bit wide memory bus in response to read or write memory commands received from the memory controller, the memory module comprising:

a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system;

logic coupled to the printed circuit board and configured to receive a first set of input address and control signals associated with a first read or write memory command and to output a first set of registered address and control signals in response to the first set of input address and control signals, the first set of input address and control signals including a first plurality of input chip select signals, the first set of registered address and control signals including a first plurality of registered chip select signals corresponding to respective ones of the first plurality of input chip select signals, the first plurality of registered chip select signals including a first registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value;

memory devices mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks, wherein the plurality of N-bit wide ranks are configured to receive respective ones of the first plurality of registered chip select signals, wherein a first N-bit wide rank in the plurality of N-bit wide ranks receiving the first registered chip select signal having the active signal value is configured to receive or output a first burst of N-bit wide data signals and a first burst of data strobes associated with the first read or write command;

circuitry coupled between data and strobe signal lines in the N-bit wide memory bus and corresponding data and strobe pins of memory devices in each of the plurality of N-bit wide ranks; and

wherein the logic is further configured to, in response to the first read or write memory command, output first control signals to the circuitry, and wherein the circuitry is configured to enable data transfers between the first rank and the memory bus through the circuitry in response to the first control signals so that respective N-bit wide data signals of the first burst of N-bit wide data signals and respective data strobes of the first burst of data strobes are transferred through the circuitry in accordance with an overall CAS latency of the memory module; and

wherein the data transfers between the first rank and the memory bus through the circuitry are registered data transfers and the circuitry is configured to add a predetermined amount of time delay for each registered data transfer through the circuitry such that the overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the memory devices.

16. The memory module of claim 15, wherein each of the memory devices has a corresponding load, and the circuitry is configured to isolate the loads of the memory devices from the memory bus.

17. The memory module of claim 15, wherein the first burst of N-bit wide data signals includes a set of consecutively transmitted data bits for each data signal line in the memory bus, and wherein the set of consecutively transmitted data bits are successively transferred through the circuitry in response to the first control signals.

18. The memory module of claim 15, wherein each of the memory devices is 4-bits wide, and wherein each of the plurality of ranks is 72-bits wide and includes 18 memory devices configured in pairs, and wherein each pair of 4-bit-wide memory devices are configured to simulate an 8-bit-wide memory device.

19. The memory module of claim 15, wherein the memory devices are organized in four ranks and the first set of input address and control signals include four chip select signals, one for each of the four ranks.

20. The memory module of claim 15, wherein the circuitry includes logic pipelines configured to enable the data transfers between the first rank and the memory bus through the circuitry in response to the first control signals.

21. The memory module of claim 15, wherein the logic is further configured to report the overall CAS latency to the memory controller in response to a mode register set command received from the memory controller.

22. The memory module of claim 15, wherein the first burst of N-bit wide data signals and the first burst of data strobes are transferred between the first N-bit wide rank and the memory controller at a specified data rate.

23. The memory module of claim 15, further comprising a phase locked loop clock driver configured to output a clock signal in response to one or more signals received from the memory controller, wherein the predetermined amount of time delay is at least one clock cycle time delay.

24. The memory module of claim 23, wherein the memory devices are dynamic random access memory devices configured to operate synchronously with the clock signal, and wherein each memory device in the first rank is configured receive or output a respective set of bits of the first burst of N-bit wide data signals on both edges of each of a respective set of data strobes of the first burst of data strobes.

25. The memory module of claim 15, wherein the logic is further configured to respond to a second set of input address and control signals associated with a second read or write memory command by outputting a second set of registered address and control signals, the second set of input address and control signals including a second plurality of input chip select signals, the second set of registered address and control signals including a second plurality of registered chip select signals corresponding to respective ones of the second plurality of input chip select signals, the second plurality of registered chip select signals including a second registered chip select signal having the active signal value and one or more other registered chip select signals each having the non-active signal value, wherein a second rank different from the first rank is configured to receive the second registered chip select signal having the active signal value and to output or receive a second burst of N-bit wide data signals and a second burst of data strobes associated with the second read or write command, wherein the logic is further configured to, in response to the second read or write memory command, output second control signals to the circuitry, and wherein the circuitry is configured to enable registered data transfers between the second rank and the memory bus through the circuitry in response to the second control signals so that the second burst of N-bit wide data signals and the second burst of data strobes are transferred between the second rank and the memory controller through the circuitry in accordance with the overall CAS latency of the memory module.

26. The memory module of claim 17, wherein the first burst of N-bit wide data signals is transferred through the circuitry in a plurality of time intervals including at least a first time interval and a last time interval, wherein the circuitry includes a set of signal paths that are enabled before the first time interval and subsequently disabled after the last time interval.

27. The memory module of claim 26, wherein:

the first read or write memory command is a read memory command;

the second read or write memory command is a write memory command;

the set of signal paths are enabled to transfer the first burst of N-bit wide data signals and the first burst of data strobes a first number of time intervals after the read memory command is received by the logic; and

the set of signal paths are enabled to transfer the second burst of N-bit wide data signals and the second burst of data strobes a second number of time intervals after the write memory command is received by the logic, the second number being different from the first number.

28. A memory module operable in a computer system to communicate data with a memory controller of the computer system via a N-bit wide memory bus in response to read or write memory commands received from the memory controller, the memory module comprising:

a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system;

logic coupled to the printed circuit board and configured to receive a set of input control and address signals associated with a read or write memory command via the memory bus and to output a set of registered control and address signals in response to the set of input control and address signals, the set of input control and address signals including a plurality of input chip select signals, the set of registered control and address signals including a plurality of registered chip select signals corresponding to respective ones of the plurality of input chip select signals, the plurality of registered chip select signals including a registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value;

memory devices mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks, wherein the plurality of N-bit wide ranks are configured to receive respective ones of the plurality of registered chip select signals, wherein a first N-bit wide rank receiving the registered chip select signal having the active signal value is configured to receive or output a first burst of N-bit wide data signals and a first burst of data strobes associated with the read/write command;

circuitry between data and data strobe signal lines in the memory bus and corresponding data and data strobe pins of the memory devices, wherein the circuitry includes logic pipelines configured to enable data transfers between the first rank and the memory bus in response to the first read or write memory command, wherein respective N-bit wide data signals of the first burst of N-bit wide data signals and respective data strobes of the first burst of data strobes are transferred between the first rank and the memory bus through the circuitry in accordance with an overall CAS latency of the memory module; and

wherein the data transfers between the first rank and the memory bus are registered data transfers; and

wherein the circuitry is configured to add a predetermined amount of time delay for each data transfer between the memory controller and the memory devices such that the overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the memory devices.

29. The memory module of claim 28, wherein the first burst of N-bit wide data signals includes a set of consecutively transmitted data bits for each data signal line in the memory bus, and wherein the circuitry includes a set of signal paths that are enabled before a first data bit of the set of consecutively transmitted data bits is transferred through the circuitry and disabled after a last data bit of the set of consecutively transmitted data bits is transferred through the circuitry.

30. The memory module of claim 28, wherein the logic is further configured to respond to a subsequent set of input address and control signals associated with a subsequent read or write memory command by outputting a subsequent set of registered address and control signals, the subsequent set of input address and control signals including a subsequent plurality of input chip select signals, the subsequent set of registered address and control signals including a subsequent plurality of registered chip select signals corresponding to respective ones of the subsequent plurality of input chip select signals, the subsequent plurality of registered chip select signals including a subsequently registered chip select signal having the active signal value and one or more other subsequently registered chip select signals each having the non-active signal value, wherein a second rank different from the first rank is configured to receive the subsequently registered chip select signal having the active signal value and to output or receive a second burst of N-bit wide data signals and a second burst of data strobes associated with the subsequent read or write command, wherein the circuitry is further configured to enable registered data transfers between the memory devices and the memory bus in response to the subsequent read/write memory command so that the second burst of N-bit wide data signals and the second burst of data strobes are transferred between the second rank and the memory bus through the circuitry.

31. The memory module of claim 28, wherein the first burst of N-bit wide data signals and the first burst of data strobes are transferred between the first N-bit wide rank and the memory controller at a specified data rate.

32. The memory module of claim 28, further comprising a phase locked loop clock driver configured to output a clock signal in response to one or more signals received from the memory controller, wherein the predetermined amount of time delay is at least one clock cycle time delay.

33. The memory module of claim 32, wherein the memory devices are dynamic random access memory devices configured to operate synchronously with the clock signal, and wherein each memory device in the first rank is configured receive or output a respective set of bits of the first burst of N-bit wide data signals on both edges of each of a respective set of data strobes of the first burst of data strobes.