Printed circuit board product with antenna structure and method for its production

• US 10,490,887 B2
• Filed: 02/23/2017
• Issued: 11/26/2019
• Est. Priority Date: 02/29/2016
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Schlaffer, Erich
• Primary Examiner(s): Aychillhum, Andargie M
• Application Number:
  US15/440,296
• Publication Number:
  US 20170250466A1
• Time in Patent Office: 1,006 Days
• Field of Search: 361748
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/48 Earthing means; Earth screens; Counterpoises
• CPC Class Codes: H01Q 19/10 using reflecting surfaces
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10098 Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
• CPC Class Codes: H05K 2203/06 Lamination
• CPC Class Codes: H05K 3/282 for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
• CPC Class Codes: H05K 3/4038 Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4697 having cavities, e.g. for mounting components H05K3/4691 takes precedence

Abstract

A method for producing an intermediate printed circuit board product (80) with an antenna structure (5), including steps of providing a ground layer (10) including optionally a release layer (20) that is removably positioned (22) on an antenna subarea (12) of an exterior side (11) of the ground layer (10); attaching a dielectric insulating layer (30) on the exterior side (11) of the ground layer (10) that is if applicable partly covered by the release layer (20); attaching a conducting layer (40) on an exterior side (31) of the dielectric insulating layer (30); laminating of the layers (10, 20, 30, 40) to receive a first semi-finished product (50); manufacturing of an antenna cavity (60) throughout the conducting layer (40) and the dielectric insulating layer (30) with a ground-plane area (62) that is if applicable made up of the release layer (20); attaching a compound signal layer (70) on the conducting layer (40) covering the antenna cavity (60); and laminating of the layers (50, 70) to receive the intermediate product (80).

Claims

1. A method for producing an intermediate printed circuit board product (80) with an antenna structure (5), comprising the following steps:

providing a ground layer (10);

optionally attaching a release layer (20) with a release layer shape (25) on one exterior side (11) of the ground layer (10), wherein the release layer (20) is removably positioned (22) on an antenna subarea (12) of the exterior side (11) of the ground layer (10);

attaching a dielectric insulating layer (30) on one exterior side (11) of the ground layer (10) that is if applicable partly covered by the release layer (20), wherein the release layer (20) is arranged between the ground layer (10) and the dielectric insulating layer (30);

attaching a conducting layer (40) on a first exterior side (31) of the dielectric insulating layer (30) opposite to the ground layer (10) wherein the dielectric insulating layer (30) is arranged between the conducting layer (40) and the ground layer (10);

laminating of the ground layer (10), the at least one dielectric insulating layer (30, 30′

), the at least one conducting layer (40, 40′

) and if applicable the release layer (20) and

optionally attaching a layer arrangement on a first exterior side (41) of said conducting layer (40), said layer arrangement comprising at least one further dielectric insulating layer (30′

, 30″

) and at least one further conducting layer (40′

, 40″

), whereby at least one further dielectric insulating layer (30′

) is attached on said first exterior side (41) of the conducting layer (40) and at least one further conducting layer (40′

) is attached on a first exterior side (31) of at least one further dielectric insulating layer (30′

, 30″

), to obtain a first semi-finished product (50);

manufacturing of at least one antenna cavity (60) within the first semi-finished product (50) starting on its exterior side (51) that is made up of the at least one conducting layer (40, 40′

) and extending throughout at least one conducting layer (40) as well as at least one dielectric insulating layer (30) with a cavity height (65) equal to the sum of at least one conducting layer height (45) and at least one dielectric insulating layer height (35), wherein if applicable a cavity projection area (61) corresponds to the release layer shape (25) and is positioned (22) on the antenna subarea (12) covered by the release layer (20) and wherein a ground-plane area (62) of the cavity (60) is made up of the release layer (20);

optionally coating (66) of the side walls (67, 68) within the antenna cavity (60);

attaching a compound signal layer (70) on the exterior side (51) made up of the conducting layer (40) of the first semi-finished product (50), wherein the compound signal layer (70) covers the antenna cavity (60); and

laminating of the first semi-finished product (50) and the compound signal layer (70) to obtain an intermediate printed circuit board product (80).

2. The method of claim 1, wherein the compound signal layer (70) comprises a dielectric no-flow prepreg layer (76) and a conducting metal layer (78) directly attached to the dielectric no-flow prepreg layer (76) wherein the dielectric no-flow prepreg layer (76) is attached to a conducting layer (40) of the first semi-finished product (50).

3. The method of claim 1, wherein the ground layer (10) is made of a laminated compound layer comprising at least two conducting metal layers (14, 16) laminated with an insulating layer (18) in between the at least two conducting metal layers (14, 16), where optionally a layer arrangement comprising at least one further insulating layer (18′

) and at least one further conducting metal layer (16′

) is stacked up and is laminated with the preceding layers to form the laminated compound layer.

4. The method of claim 1, wherein the antenna cavity (60) has a vent through-hole (69) arranged between the ground-plane area (62) of the cavity (60) and an exterior side (82) of the intermediate printed circuit board product (80).

5. The method of claim 1, wherein the antenna cavity (60) is surrounded with shielding vias (110) that are arranged within the laminated ground layer (10) and/or at least one dielectric insulating layer (30) and/or at least one conducting layer (40) and/or compound signal layer (70) in a distance (115) in regard to the antenna cavity (60).

6. The method of claim 1, wherein the antenna structure (5) comprises an antenna design area (6) that is arranged on an exterior side (71) of the compound signal layer (70).

7. The method of claim 1, wherein a digital processing area (105) with a digital processing structure (100) comprising at least one signal processing unit (101) is mounted on or embedded within the intermediate printed circuit board product (80) in a distance (125) in regard to the antenna cavity (60), whereby the signal processing unit (101) is connected via at least one antenna signal line (104) with the antenna structure (5) and is designed for analogue and digital signal processing of antenna signals.

8. The method of claim 1, wherein solder masks (91, 92) are affixed on one or both exterior sides (81, 82) of one intermediate printed circuit board product (80) or on one or both exterior sides (81, 82) of at least two previously interconnected and stacked-up intermediate printed circuit board products (80).

9. A method for producing an intermediate printed circuit board product (80) with an antenna structure (5), comprising the following steps:

providing a ground layer (10);

attaching a dielectric insulating layer (30) on one exterior side (11) of the ground layer (10), wherein the dielectric insulating layer (30) has at least one recess (39) extending throughout the dielectric insulating layer height (35) of the dielectric insulating layer (30), and wherein the at least one recess (39) is positioned on an antenna subarea (12) of the exterior side (11) of the ground layer (10);

attaching a conducting layer (40) on a first exterior side (31) of the dielectric insulating layer (30) opposite to the ground layer (10), wherein the dielectric insulating layer (30) is arranged between the conducting layer (40) and the ground layer (10), and wherein the conducting layer (40) preferably has at least one recess (49) extending throughout the conducting layer height (45) of the conducting layer (40) which at least one recess (49) is positioned coextensive with the at least one recess (39) of the dielectric insulating layer (30);

laminating of the ground layer (10), the at least one dielectric insulating layer (30) and the at least one conducting layer (40) and

optionally attaching a layer arrangement on a first exterior side (41) of said conducting layer (40), said layer arrangement comprising at least one further dielectric insulating layer (30′

, 30″

) and at least one further conducting layer (40′

, 40″

), whereby at least one further dielectric insulating layer (30′

, 30″

) is attached on said first exterior side (41) of the conducting layer (40) and at least one further conducting layer (40′

) is attached on a first exterior side (31) of at least one further dielectric insulating layer (30′

), and wherein preferably at least one further dielectric insulating layer (30′

, 30″

) and at least one further conducting layer (40′

, 40″

) has at least one recess (39, 49) that is positioned in registry with at least one of the preceding recesses (39, 49) as well as in registry with an antenna subarea (12) on the exterior side (11) of the ground layer (10), to obtain a first semi-finished product (50);

receiving at least one antenna cavity (60) within the first semi-finished product (50) starting on its exterior side (51) that is made up of the recess (49) of at least one conducting layer (40) as well as the coextensive recess (39) of at least one dielectric insulating layer (30), the at least one antenna cavity (60) comprising a cavity height (65) equal to the sum of at least one conducting layer height (45) and at least one dielectric insulating layer height (35), wherein a cavity projection area (65) of the antenna cavity (60) is positioned (22) on the antenna subarea (12);

optionally coating (66) of the side walls (67, 68) within the antenna cavity (60);

attaching a compound signal layer (70) on the exterior side (51) made up of the conducting layer (40) of the first semi-finished product (50), wherein the compound signal layer (70) covers the at least one antenna cavity (60); and

laminating of the first semi-finished product (50) and the compound signal layer (70) to obtain an intermediate printed circuit board product (80).

10. The method of claim 9, wherein the compound signal layer (70) comprises a dielectric no-flow prepreg layer (76) and a conducting metal layer (78) directly attached to the dielectric no-flow prepreg layer (76) wherein the dielectric no-flow prepreg layer (76) is attached to a conducting layer (40) of the first semi-finished product (50).

11. The method of claim 9, wherein the ground layer (10) is made of a laminated compound layer comprising at least two conducting metal layers (14, 16) laminated with an insulating layer (18) in between the at least two conducting metal layers (14, 16), where optionally a layer arrangement comprising at least one further insulating layer (18′

) and at least one further conducting metal layer (16′

) is stacked up and is laminated with the preceding layers to form the laminated compound layer.

12. The method of claim 9, wherein the antenna cavity (60) has a vent through-hole (69) arranged between the ground-plane area (62) of the cavity (60) and an exterior side (82) of the intermediate printed circuit board product (80).

13. The method of claim 9, wherein the antenna cavity (60) is surrounded with shielding vias (110) that are arranged within the laminated ground layer (10) and/or at least one dielectric insulating layer (30) and/or at least one conducting layer (40) and/or compound signal layer (70) in a distance (115) in regard to the antenna cavity (60).

14. The method of claim 9, wherein the antenna structure (5) comprises an antenna design area (6) that is arranged on an exterior side (71) of the compound signal layer (70).

15. The method of claim 9, wherein a digital processing area (105) with a digital processing structure (100) comprising at least one signal processing unit (101) is mounted on or embedded within the intermediate printed circuit board product (80) in a distance (125) in regard to the antenna cavity (60), whereby the signal processing unit (101) is connected via at least one antenna signal line (104) with the antenna structure (5) and is designed for analogue and digital signal processing of antenna signals.

16. The method of claim 9, wherein solder masks (91, 92) are affixed on one or both exterior sides (81, 82) of one intermediate printed circuit board product (80) or on one or both exterior sides (81, 82) of at least two previously interconnected and stacked-up intermediate printed circuit board products (80).

17. An intermediate printed circuit board product (80) with an antenna structure (5), wherein at least one antenna cavity (60) is arranged within a first semi-finished product (50) comprising:

at least one ground layer (10);

at least one dielectric insulating layer (30) which is attached to the ground layer (10); and

at least one conducting layer (40) which is attached to the dielectric insulating layer (30) opposite to the ground layer (10) in a way that the at least one dielectric insulating layer (30) is arranged between the at least one conducting layer (40) and the ground layer (10),

whereby the ground layer (10), the at least one dielectric insulating layer (30) and the at least one conducting layer (40) are laminated, and

wherein the antenna cavity (60) touches the ground layer (10) alongside a ground-plane area (62) and extends throughout the at least one conducting layer (40) as well as the at least one dielectric insulating layer (30) with a cavity height (65) equal to the sum of at least one conducting layer height (45) and of at least one dielectric insulating layer height (35), wherein a compound signal layer (70) is attached on the conducting layer (40) of the first semi-finished product (50) covering the antenna cavity (60), and the first semi-finished product (50) and the compound signal layer (70) are laminated.

18. The intermediate printed circuit board product (80) of claim 17, wherein the antenna cavity (60) is surrounded with shielding vias (110) that are arranged within the ground layer (10) and/or dielectric insulating layer (30) and/or conducting layer (40) and/or compound signal layer (70) in a distance (115) to the antenna cavity (60).

19. The intermediate printed circuit board product (80) of claim 17, wherein the compound signal layer (70) comprises a dielectric no-flow prepreg layer (76) and a conducting metal layer (78) directly attached to the dielectric no-flow prepreg layer (76) wherein the dielectric no-flow prepreg layer (76) is attached to a conducting layer (40) of the first semi-finished product (50).

20. The intermediate printed circuit board product (80) of claim 17, wherein a digital processing area (105) with a digital processing structure (100) comprising at least one signal processing unit (101) that is mounted on or embedded within the intermediate printed circuit board product (80) in a distance (125) to the antenna cavity (60), whereby the processing unit (101) is connected via at least one antenna signal line (104) with the antenna structure (5) and is designed for analogue and digital signal processing of antenna signals.

21. The intermediate printed circuit board product (80) of claim 17, wherein at least one antenna cavity (60) has a vent through-hole (69) starting from the ground-plane area (62) and passing throughout the laminated ground layer (10).

22. A printed circuit board (1) with an antenna structure (5) comprising:

at least one intermediate printed circuit board product (80) of claim 17; and

a solder mask (91, 92) applied on one or both exterior sides (81, 82) of the at least one intermediate printed circuit board product (80) or on one or both exterior sides (81, 82) of at least two previously interconnected and stacked-up intermediate printed circuit board products (80).